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publication# 20446 rev: j amendment/ 0 issue date: april 2002 mach 5 cpld family fifth generation mach architecture features high logic densities and i/os for increased logic integration 128 to 512 macrocell densities 68 to 256 i/os wide selection of density and i/o combinations to support most application needs ? macrocell density options ? i/o options ? p to 4 i/o options per macrocell density ? p to 5 density & i/o options for each package performance features to ? system needs 5.5 ns t pd commercial, 7.5 ns t pd industrial 182 mhz f cnt four programmable power/speed settings per block flexible architecture facilitates logic design ? ultiple levels of switch matrices allow for performance-based routing 100% routability and pin-out retention synchronous and asynchronous clocking, including dual-edge clocking ? synchronous product- or sum-term set or reset 16 to 64 output enables functions of up to 32 product terms advanced capabilities for easy system integration 3.3-v & 5-v jedec-compliant operations ieee 1149.1 compliant for boundary scan testing 3.3-v & 5-v in-system programmable via ieee 1149.1 boundary scan test access port pci compliant (-5/-6/-7/-10/-12 speed grades) safe for mixed supply voltage system design bus-friendly inputs & i/os individual output slew rate control ? ot socketing programmable security bit advanced e 2 cmos process provides high performance, cost effective solutions
2m ach 5 family note: 1. ?5-xxx?is for 5-v devices. ?5lv-xxx?is for 3.3-v devices. general description the mach 5 family consists of a broad range of high-density and high-i/o complex programmable logic devices (cplds). the ?th-generation mach architecture yields fast speeds at high cpld densities, low power, and supports additional features such as in-system programmability, boundary scan testability, and advanced clocking options (table 1). the mach 5 family offers 5-v (m5-xxx) and 3.3-v (m5lv-xxx) operation. manufactured in state-of-the-art iso 9000 quali?d fabrication facilities on e 2 cmos process technologies, mach 5 devices are available with pin-to-pin delays as fast as 5.5 ns (table 2). the 5.5, 6.5, 7.5, 10, and 12-ns devices are compliant with the pci local bus speci?ation . t able 1. mach 5 device features 1 feature m5-128/1 m5lv-128 m5-192/1 m5-256/1 m5lv-256 m5-320 m5lv-320 m5-384 m5lv-384 m5-512 m5lv-512 supply voltage (v) 5 3.3 5 5 3.3 5 3.3 5 3.3 5 3.3 macrocells 128 128 192 256 256 320 320 384 384 512 512 maximum user i/o pins 120 120 120 160 160 192 160 160 160 256 256 t pd (ns) 5.5 5.5 5.5 5.5 5.5 6.5 6.5 6.5 6.5 6.5 6.5 t ss (ns) 3.0 3.0 3.0 3.0 3.0 3.0 3.0 3.0 3.0 3.0 3.0 t cos (ns) 4.5 4.5 4.5 4.5 4.5 5.0 5.0 5.0 5.0 5.0 5.0 f cnt (mhz) 182 182 182 182 182 167 167 167 167 167 167 t ypical static power (ma) 35 35 45 55 55 70 70 75 75 100 100 ieee 1149.1 boundary scan compliant yes yes yes yes yes yes yes yes yes yes yes pci-compliant yes yes yes yes yes yes yes yes yes yes yes
mach 5 family 3 note: 1. c = commercial grade, i = industrial grade 2. /1 version recommended for new designs w ith lattice? unique hierarchical architecture, the mach 5 family provides densities up to 512 macrocells to support full system logic integration. extensive routing resources ensure pinout retention as well as high utilization. it is ideal for pal block device integration and a wide range of other applications including high-speed computing, low-power applications, communications, and embedded control. at each macrocell density point, lattice offers several i/o and package options to meet a wide range of design needs (table 3). note: 1. the i/o options indicated with a ??are obsolete, please contact factory for more information. advanced power management options allow designers to incrementally reduce power while maintaining the level of performance needed for today? complex designs. i/o safety features t able 2. mach 5 speed grades device speed grade 1 -5 -6 -7 -10 -12 -15 -20 m5-128 2 c c, i c, i c, i i m5-128/1 c c, i c, i c, i c, i i m5lv-128 c c,i c, i c, i i m5-192/1 c c, i c, i c, i c, i i m5-256 2 c c, i c, i c, i i m5-256/1 c c, i c, i c, i c, i i m5lv-256 c c, i c, i c, i i m5-320 c c, i c, i c, i c, i i m5lv-320 c c, i c, i c, i c, i i m5-384 c c, i c, i c, i c, i i m5lv-384 c c, i c, i c, i c, i i m5-512 c c, i c, i c, i c, i i m5lv-512 c c, i c, i c, i c, i i t able 3. mach 5 package and i/o options 1 m5-128/1 m5lv-128 m5-192/1 m5-256/1 m5lv-256 m5-320 m5lv-320 m5-384 m5lv-384 m5-512 m5lv-512 supply voltage 5 3.3 5 5 3.3 5 3.3 5 3.3 5 3.3 100-pin tqfp 68 68, 74 68 68 68*, 74 100-pin pqfp 68 68* 68* 68* 68 144-pin tqfp 104 104 144-pin pqfp 104 104* 104* 104* 104* 160-pin pqfp 120 120 120 120 120 120* 120 120* 120 120* 120 208-pin pqfp 160 160 160 160 160 160 160 160 240-pin pqfp 184* 184* 184* 184* 184* 184* 256-ball bga 192 192* 192* 192* 192* 192* 352-ball bga 256 256
4m ach 5 family allow for mixed-voltage design, and both the 3.3-v and the 5-v device versions are in-system programmable through an ieee 1149.1 test access port (tap) interface. functional description the mach 5 architecture consists of pal blocks connected by two levels of interconnect. the block interconnect provides routing among 4 pal blocks. this grouping of pal blocks joined by the block interconnect is called a segment . the second level of interconnect, the segment interconnect , ties all of the segments together. the only logic difference between any two mach 5 devices is the number of segments. therefore, once a designer is familiar with one device, consistent performance can be expected across the entire family. all devices have four clock pins available which can also be used as logic inputs. the mach 5 pal blocks consist of the elements listed below (figure 2). while each pal block resembles an independent pal device, it has superior control and logic generation capabilities. i/o cells product-term array and logic allocator macrocells register control generator output enable generator i/o cells the i/os associated with each pal block have a path directly back to that pal block called local feedback . if the i/o is used in another pal block, the interconnect feeder assigns a block interconnect line to that signal. the interconnect feeder acts as an input switch matrix. the block and segment interconnects provide connections between any two signals in a device. the block feeder assigns block interconnect lines and local feedback lines to the pal block inputs. block interconnect 4 clk block: 16 mcs segment: 4 blocks segment interconnect 20446g-001 figure 1. mach 5 block diagram
mach 5 family 5 product-term array and logic allocator the product-term array uses the same sum-of-products architecture as pal devices and consists of 32 inputs (plus their complements) and 64 product terms arranged in 16 clusters . a cluster is a sum- of-products function with either 3 of 4 product terms. logic allocators assign the clusters to macrocells. each macrocell can accept up to eight clusters of three or four product terms, but a given cluster can only be steered to one macrocell (table 4). if only three product terms in a cluster are steered, the fourth can be used as an input to an xor gate for separate logic generation and/or polarity control. the wide logic allocator is comprised of all 16 of the individual logic allocators and acts as an output switch matrix by reassigning logic to macrocells to retain pinout as designs change. the logic allocation scheme in the mach 5 device allows for the implementation of large equations (up to 32 product terms) with only one pass through the logic array. t able 4. product term steering options for pt clusters and macrocells macrocell available clusters macrocell available clusters m 0 c 0 , c 1 , c 2 , c 3 , c 4 m 8 c 5 , c 6 , c 7 , c 8 , c 9 , c 10 , c 11 , c 12 m 1 c 0 , c 1 , c 2 , c 3 , c 4 , c 5 m 9 c 6 , c 7 , c 8 , c 9 , c 10 , c 11 , c 12 , c 13 m 2 c 0 , c 1 , c 2 , c 3 , c 4 , c 5 , c 6 m 10 c 7 , c 8 , c 9 , c 10 , c 11 , c 12 , c 13 , c 14 m 3 c 0 , c 1 , c 2 , c 3 , c 4 , c 5 , c 6 , c 7 m 11 c 8 , c 9 , c 10 , c 11 , c 12 , c 13 , c 14 , c 15 m 4 c 0 , c 1 , c 2 , c 3 , c 4 , c 5 , c 6 , c 7 m 12 c 8 , c 9 , c 10 , c 11 , c 12 , c 13 , c 14 , c 15 m 5 c 1 , c 2 , c 3 , c 4 , c 5 , c 6 , c 7 , c 8 m 13 c 9 , c 10 , c 11 , c 12 , c 13 , c 14 , c 15 m 6 c 2 , c 3 , c 4 , c 5 , c 6 , c 7 , c 8 , c 9 m 14 c 10 , c 11 , c 12 , c 13 , c 14 , c 15 m 7 c 3 , c 4 , c 5 , c 6 , c 7 , c 8 , c 9 , c 10 m 15 c 11 , c 12 , c 13 , c 14 , c 15 block interconnect interconnect feeder block feeder 32 i/os 16 2 macrocells logic alocator control generator oe generator product-term array 32 32 input register path 2 local feedback 20446g-002 figure 2. pal block structure
6m ach 5 family macrocells the macrocells for mach 5 devices consist of a storage element which can be con?ured for combinatorial, registered or latched operation (figure 3). the d-type ?p-?ps can be con?ured as t-type, j-k, or s-r operation through the use of the xor gate associated with each macrocell. each pal block has the capability to provide two input registers by using macrocells 0 and 15. in order to use this option, these macrocells must be accessed via the i/o pins associated with macrocells 3 and 12, respectively. once the macrocell is used as an input register, it cannot be used for logic, so its clusters can be re-directed through the logic allocator to another macrocell. the i/o pins associated with macrocells 0 and 15 can still be used as input pins. although the i/o pins for macrocells 3 and 12 are used to connect to the input registers, these macrocells can still be used as ?uried?macrocells to drive device logic via the matrix. control generator the control generator provides four congurable cl ock lines and three con?urable set/reset lines to each macrocell in a pal block. any of the four clock lines and any of the three set/reset lines can be independently selected by any ?p-?p within a block. the clock lines can be con?ured to provide synchronous global (pin) clocks and asynchronous product term clocks, sum term clocks, and latch enables (figure 4). three of the four global clocks, as well as two product-term clocks and one sum-term clock, are available per pal block. positive or negative edge clocking is available as well as advanced clocking features such as complementary and biphase clocking. complementary clocking provides two clock lines exactly 180 degrees out of phase, and is useful in applications such as fast data paths. a biphase clock line clocks ?p-?ps on both the positive and negative edges of the clock. the con?uration options for the four clock lines per pal block are as follows: clock line 0 options global clock (0, 1, 2, or 3) with positive or negative edge clock enable product-term clock (a*b*c) sum-term clock (a+b+c) logic allocator 5-8 clusters/ mc prog. polarity mode selection control bus macrocell d q 20446g-003 figure 3. macrocell diagram
mach 5 family 7 clock line 1 options global clock (0, 1, 2, or 3) with positive edge clock enable global clock (0, 1, 2, or 3) with negative edge clock enable global clock (0, 1, 2, or 3) with positive and negative edge clock enable (biphase) clock line 2 options global clock (0, 1, 2, or 3) with clock enable clock line 3 options complement of clock line 2 (same clock enable) product-term clock (if clock line 2 does not use clock enable the set/reset generation portion of the control generator (figure 5) creates three set/reset lines for the pal block. each macrocell can choose one of these three lines or choose no set/reset at all. all three lines can be con?ured for product term set/reset and two of the three lines can be con?ured as sum term set/reset and one of the lines can be con?ured as product-term or sum- term latch enable. while the set/reset signals are generated in the control generator, whether that signal sets or resets a ?p-?p is determined within the individual macrocell. the same signal can set one ?p-?p and reset another. pt2 or /pt2 can also be used as a latch enable for macrocells con?ured as latches. 0 1 2 3 0 1 2 3 0 1 2 3 clkin clock enable n (0) n (1) out mux 2to1 /clk f0 /clk clk clken1 biphase clken2 out clk0 clk1 clk2 clk3 clkin clock enable mux 2to1 /clk2 ptclk f0 block clocks 0?3 pt (0:3) pinclk (0:3) pt0 pt1 pt2 pt3 mux 4to1 in (0) in (1) in (2) in (3) out u1 f0 f1 mux 4to1 in (0) in (1) in (2) in (3) out u2 f0 f1 mux 4to1 in (0) in (1) in (2) in (3) out u3 f0 f1 mux 2to1 mux 2to1 f0 20446g-004 figure 4. clock generator set2/rst2/le block sets/reset 0?2, le pt (0:2) pt0 pt1 pt2 set1/rst1 set0/rst0 mux 2to1 out f0 pt1 /pt1(st) mux 2to1 out f0 pt2 /pt2 20446g-005 figure 5. set/reset generator
8m ach 5 family oe generator there is one output enable (oe) generator per pal block that generates two product-term driven output enables. each i/o cell is simply an output buffer. each i/o cell within the pal block can choose to be permanently enabled, permanently disabled, or choose one of the two product term output enables per pal block (figure 6). output enable generator v cc internal feedback external feedback 20446g-006 figure 6. output enable generator and i/o cell
mach 5 family 9 mach 5 timing model the primary focus of the mach 5 timing model is to accurately represent the timing in a mach 5 device, and at the same time, be easy to understand. this model accurately describes all combinatorial and registered paths through the device, making a distinction between internal feedback and external feedback . a signal uses internal feedback when it is fed back into the switch matrix or block without having to go through the output buffer. the input register speci?ations are also reported as internal feedback. when a signal is fed back into the switch matrix after having gone through the output buffer, it is using external feedback. the parameter, t buf , is de?ed as the time it takes to go through the output buffer to the i/o pad. if a signal goes to the internal feedback rather than to the i/o pad, the parameter designator is followed by an ?? by adding t buf to this internal parameter, the external parameter is derived. for example, t pd = t pdi + t buf . a diagram representing the modularized mach 5 timing model is shown in figure 7. refer to the technical note entitled mach 5 timing and high speed design for a more detailed discussion about the timing parameters. input reg/ input latch t sir (s/a) t hir (s/a) t sil t hil t srr t ces t ceh t co (s/a) i t pdili t goai t sri t blk t seg ce sr (external feedback) (internal feedback) q t s (s/a) t h (s/a) t sal t hal t srr t ces t ceh t pdi t co (s/a) i t pdli t goai t sri comb/dff/ latch ce sr t pl1 t pl2 t pl3 in out t pt t ea t er t b uf t slw pin clk q 20446g-014 figure 7. mach 5 timing model
10 mach 5 family multiple i/o and density options the mach 5 family offers six macrocell densities in a number of i/o options. this allows designers to choose a device close to their logic density and i/o requirements, thus minimizing costs. for the same package type, every density has the same pin-out. with proper design considerations, a design can be moved to a higher or lower density part as required. ieee 1149.1 - compliant boundary scan testability most mach 5 devices have boundary scan registers and are compliant to the ieee 1149.1 standard. this allows functional testing of the circuit board on which the device is mounted through a serial scan path that can access all critical logic nodes. internal registers are linked internally, allowing test data to be shifted in and loaded directly onto test nodes, or test node data to be captured and shifted out for veri?ation. in addition, these devices can be linked into a board-level serial scan path for more complete board-level testing. ieee 1149.1 - compliant in-system programming programming devices in-system provides a number of signi?ant bene?s including: rapid prototyping, lower inventory levels, higher quality, and the ability to make in-?ld modi?ations. all mach 5 devices provide in-system programming (isp) capability through their ieee 1149.1- compliant boundary scan test access port. by using the ieee 1149.1-compliant boundary scan t est access port as the communication interface through which isp is achieved, customers get the bene? of a standard, well-de?ed interface. mach 5 devices can be programmed across the commercial temperature and voltage range. the pc-based latticepro software facilitates in-system programming of mach 5 devices. latticepro software takes the jedec ?e output produced by design implementation software, along with information about the boundary scan chain, and creates a set of vectors that are used to drive the boundary scan chain. latticepro software can use these vectors to drive a boundary scan chain via the parallel port of a pc. alternatively, latticepro software can output ?es in formats understood by common automated test equipment. this equipment can then be used to program mach 5 devices during the testing of a circuit board. pci compliant mach 5 devices in the -5/-6/-7/-10/-12 speed grades are compliant with the pci local bus speci?ation version 2.1, published by the pci special interest group (sig). the 5-v devices are fully pci-compliant. the 3.3-v devices are mostly compliant but do not meet the pci condition to clamp the inputs as they rise above v cc because of their 5-v input tolerant feature. mach 5 devices provide the speed, drive, density, output enables and i/os for the most complex pci designs.
mach 5 family 11 safe for mixed supply voltage system designs 1 both the 3.3-v and 5-v v cc mach 5 devices are safe for mixed supply voltage system designs. the 5-v devices will not overdrive 3.3-v devices above the output voltage of 3.3 v, while they accept inputs from other 3.3-v devices. the 3.3-v devices will accept inputs up to 5.5 v. both the 3.3-v and 5-v versions have the same high-speed performance and provide easy-to-use mixed- voltage design capability. note: 1. excludes original m5-128, m5-192, and m5-256 while m5-128/1, m3-192/1 and m5-256/1 are supported. please refer to application note titled ?ot socketing and mixed supply design with mach 4 and mach 5 devices? bus-friendly inputs and i/os all mach 5 devices have inputs and i/os which feature the bus-friendly circuitry incorporating two inverters in series which loop back to the input. this double inversion weakly holds the input at its last driven logic state. while it is a good design practice to tie unused pins to a known state, the bus-friendly input structure pulls pins away from the input threshold voltage where noise can cause high-frequency switching. at power-up, the bus-friendly latches are reset to a logic level ?.?fo r the circuit diagram, please refer to the document entitled mach endurance characteristics on the lattice data book cd-rom or lattice web site. power management there are 4 power/speed options in each mach 5 pal block (table 5). the speed and power tradeoff can be tailored for each design. the signal speed paths in the lower-power pal blocks will be slower than those in the higher-power pal blocks. this feature allows speed critical paths to run at maximum frequency while the rest of the signal paths operate in a lower-power mode. in large designs, there may be several different speed requirements for different portions of the design. programmable slew rate each mach 5 device i/o has an individually programmable output slew rate control bit. each output can be individually con?ured for the higher speed transition (3 v/ns) or for the lower noise transition (1 v/ns). for high-speed designs with long, unterminated traces, the slow-slew rate will introduce fewer re?ctions, less noise, and keep ground bounce to a minimum. for designs with short traces or well terminated lines, the fast slew rate can be used to achieve the highest speed. the slew rate is adjusted independent of power. power-up reset/set all ?p-?ps power up to a known state for predictable system initialization. if a macrocell is con?ured to set on a signal from the control generator, then that macrocell will be set during device power-up. if a macrocell is con?ured to reset on a signal from the control generator or is not con?ured for set/reset, then that macrocell will reset on power-up. to guarantee t able 5. power levels high speed/high power 100% power medium high speed/medium high power 67% power medium low speed/medium low power 40% power low speed/low power 20% power
12 mach 5 family initialization values, the v cc rise must be monotonic and the clock must be inactive until the reset delay time has elapsed. security bit a programmable security bit is provided on the mach 5 devices as a deterrent to unauthorized copying of the array con?uration patterns. once programmed, this bit defeats readback of the programmed pattern by a device programmer, securing proprietary designs from competitors. programming and veri?ation are also defeated by the security bit. the bit can only be reset by erasing the entire device.
mach 5 family 13 mach 5 pal block 04 8121620242832 i/o cell i/o switch matrix output enable output enable clk i/o cell i/o cell i/o cell i/o cell i/o cell i/o cell i/o cell i/o cell i/o cell i/o cell i/o cell i/o cell i/o cell i/o cell i/o cell macro cell macro cell macro cell macro cell macro cell macro cell macro cell macro cell 32 macro cell macro cell macro cell macro cell macro cell macro cell macro cell macro cell 7 0 logic allocator 63 c 0 c 1 c 2 c 3 c 4 c 5 c 6 c 7 c 8 c 9 c 10 c 11 c 12 c 13 c 14 c 15 m 3 m 6 m 5 m 4 m 2 m 1 m 0 m 9 m 8 m 7 m 10 m 11 m 12 m 13 m 14 m 15 i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o control generator 16 16 4 63 36 40 44 48 52 56 60 04 8121 620242832 63 36 40 44 48 52 56 60 20446g-015
14 mach 5 family block diagram ?m5(lv)-128/xxx macrocells 64 x 73 and logic array and logic allocator control generator 64 pt 2 pt oe i/o cells 16 16 32 7 pt 7 2 32 16 macrocells 64 x 73 and logic array and logic allocator control generator 64 pt 2 pt oe i/o cells 16 16 32 7 pt 7 2 32 16 macrocells control generator 64 pt 2 pt oe 16 16 32 7 pt 7 2 32 16 i/o cells 64 x 73 and logic array and logic allocator macrocells control generator 64 pt 2 pt oe 16 16 32 7 pt 7 2 32 16 i/o cells 64 x 73 and logic array and logic allocator block a/macrocells 0-15 block d/macrocells 0-15 block b/macrocells 0-15 block c/macrocells 0-15 block interconnect macrocells 64 x 73 and logic array and logic allocator control generator 64 pt 2 pt oe i/o cells 16 16 32 7 pt 7 2 32 16 macrocells 64 x 73 and logic array and logic allocator control generator 64 pt 2 pt oe i/o cells 16 16 32 7 pt 7 2 32 16 macrocells control generator 64 pt 2 pt oe 16 16 32 7 pt 7 2 32 16 i/o cells 64 x 73 and logic array and logic allocator macrocells control generator 64 pt 2 pt oe 16 16 32 7 pt 7 2 32 16 i/o cells 64 x 73 and logic array and logic allocator block a/macrocells 0-15 block d/macrocells 0-15 block b/macrocells 0-15 block c/macrocells 0-15 block interconnect s e g m e n t i n t e r c o n n e c t clk0 clk1 clk2 clk3 4 segment 0 segment 1 i 0, 1 i 2, 3 2 2 20446g-007
mach 5 family 15 block diagram ?m5-192/xxx macrocells 64 x 73 and logic array and logic allocator control generator 64 pt 2 pt oe i/o cells 16 16 32 7 pt 7 2 32 16 macrocells 64 x 73 and logic array and logic allocator control generator 64 pt 2 pt oe i/o cells 16 16 32 7 pt 7 2 32 16 macrocells control generator 64 pt 2 pt oe 16 16 32 7 pt 7 2 32 16 i/o cells 64 x 73 and logic array and logic allocator macrocells control generator 64 pt 2 pt oe 16 16 32 7 pt 7 2 32 16 i/o cells 64 x 73 and logic array and logic allocator block a/macrocells 0-15 block d/macrocells 0-15 block b/macrocells 0-15 block c/macrocells 0-15 block interconnect macrocells 64 x 73 and logic array and logic allocator control generator 64 pt 2 pt oe i/o cells 16 16 32 7 pt 7 2 32 16 macrocells 64 x 73 and logic array and logic allocator control generator 64 pt 2 pt oe i/o cells 16 16 32 7 pt 7 2 32 16 macrocells control generator 64 pt 2 pt oe 16 16 32 7 pt 7 2 32 16 i/o cells 64 x 73 and logic array and logic allocator 2 macrocells control generator 64 pt 2 pt oe 16 16 32 7 pt 7 2 32 16 i/o cells 64 x 73 and logic array and logic allocator block a/macrocells 0-15 block d/macrocells 0-15 block b/macrocells 0-15 block c/macrocells 0-15 block interconnect macrocells 64 x 73 and logic array and logic allocator control generator 64 pt 2 pt oe i/o cells 16 16 32 7 pt 7 2 32 16 macrocells 64 x 73 and logic array and logic allocator control generator 64 pt 2 pt oe i/o cells 16 16 32 7 pt 7 2 32 16 macrocells control generator 64 pt 2 pt oe 16 16 32 7 pt 7 2 32 16 i/o cells 64 x 73 and logic array and logic allocator macrocells control generator 64 pt 2 pt oe 16 16 32 7 pt 7 2 32 16 i/o cells 64 x 73 and logic array and logic allocator block a/macrocells 0-15 block d/macrocells 0-15 block b/macrocells 0-15 block c/macrocells 0-15 block interconnect s e g m e n t i n t e r c o n n e c t clk0 clk1 clk2 clk3 4 segment 0 segment 2 segment 1 i 0 i 2, i 3 i 1 20446g-008
16 mach 5 family block diagram ?m5(lv)-256/xxx macrocells 64 x 73 and logic array and logic allocator control generator 64 pt 2 pt oe i/o cells 16 16 32 7 pt 7 2 32 16 macrocells 64 x 73 and logic array and logic allocator control generator 64 pt 2 pt oe i/o cells 16 16 32 7 pt 7 2 32 16 macrocells control generator 64 pt 2 pt oe 16 16 32 7 pt 7 2 32 16 i/o cells 64 x 73 and logic array and logic allocator macrocells control generator 64 pt 2 pt oe 16 16 32 7 pt 7 2 32 16 i/o cells 64 x 73 and logic array and logic allocator block a/macrocells 0-15 block d/macrocells 0-15 block b/macrocells 0-15 block c/macrocells 0-15 block interconnect macrocells 64 x 73 and logic array and logic allocator control generator 64 pt 2 pt oe i/o cells 16 16 32 7 pt 7 2 32 16 macrocells 64 x 73 and logic array and logic allocator control generator 64 pt 2 pt oe i/o cells 16 16 32 7 pt 7 2 32 16 macrocells control generator 64 pt 2 pt oe 16 16 32 7 pt 7 2 32 16 i/o cells 64 x 73 and logic array and logic allocator macrocells control generator 64 pt 2 pt oe 16 16 32 7 pt 7 2 32 16 i/o cells 64 x 73 and logic array and logic allocator block a/macrocells 0-15 block d/macrocells 0-15 block b/macrocells 0-15 block c/macrocells 0-15 block interconnect macrocells 64 x 73 and logic array and logic allocator control generator 64 pt 2 pt oe i/o cells 16 16 32 7 pt 7 2 32 16 macrocells 64 x 73 and logic array and logic allocator control generator 64 pt 2 pt oe i/o cells 16 16 32 7 pt 7 2 32 16 macrocells control generator 64 pt 2 pt oe 16 16 32 7 pt 7 2 32 16 i/o cells 64 x 73 and logic array and logic allocator macrocells control generator 64 pt 2 pt oe 16 16 32 7 pt 7 2 32 16 i/o cells 64 x 73 and logic array and logic allocator block a/macrocells 0-15 block d/macrocells 0-15 block b/macrocells 0-15 block c/macrocells 0-15 block interconnect macrocells 64 x 73 and logic array and logic allocator control generator 64 pt 2 pt oe i/o cells 16 16 32 7 pt 7 2 32 16 macrocells 64 x 73 and logic array and logic allocator control generator 64 pt 2 pt oe i/o cells 16 16 32 7 pt 7 2 32 16 macrocells control generator 64 pt 2 pt oe 16 16 32 7 pt 7 2 32 16 i/o cells 64 x 73 and logic array and logic allocator macrocells control generator 64 pt 2 pt oe 16 16 32 7 pt 7 2 32 16 i/o cells 64 x 73 and logic array and logic allocator block a/macrocells 0-15 block d/macrocells 0-15 block b/macrocells 0-15 block c/macrocells 0-15 block interconnect s e g m e n t i n t e r c o n n e c t clk0 clk1 clk2 clk3 4 segment 0 segment 3 segment 2 segment 1 i 0 i 3 i 1 i 2 20446g-009
mach 5 family 17 block diagram ?m5(lv)-320/xxx macrocells 64 x 73 and logic array and logic allocator control generator 64 pt 2 pt oe i/o cells 16 16 32 7 pt 7 2 32 16 macrocells 64 x 73 and logic array and logic allocator control generator 64 pt 2 pt oe i/o cells 16 16 32 7 pt 7 2 32 16 macrocells control generator 64 pt 2 pt oe 16 16 32 7 pt 7 2 32 16 i/o cells 64 x 73 and logic array and logic allocator macrocells control generator 64 pt 2 pt oe 16 16 32 7 pt 7 2 32 16 i/o cells 64 x 73 and logic array and logic allocator block a/macrocells 0-15 block d/macrocells 0-15 block b/macrocells 0-15 block c/macrocells 0-15 block interconnect macrocells 64 x 73 and logic array and logic allocator control generator 64 pt 2 pt oe i/o cells 16 16 32 7 pt 7 2 32 16 macrocells 64 x 73 and logic array and logic allocator control generator 64 pt 2 pt oe i/o cells 16 16 32 7 pt 7 2 32 16 macrocells control generator 64 pt 2 pt oe 16 16 32 7 pt 7 2 32 16 i/o cells 64 x 73 and logic array and logic allocator macrocells control generator 64 pt 2 pt oe 16 16 32 7 pt 7 2 32 16 i/o cells 64 x 73 and logic array and logic allocator block a/macrocells 0-15 block d/macrocells 0-15 block b/macrocells 0-15 block c/macrocells 0-15 block interconnect macrocells 64 x 73 and logic array and logic allocator control generator 64 pt 2 pt oe i/o cells 16 16 32 7 pt 7 2 32 16 macrocells 64 x 73 and logic array and logic allocator control generator 64 pt 2 pt oe i/o cells 16 16 32 7 pt 7 2 32 16 macrocells control generator 64 pt 2 pt oe 16 16 32 7 pt 7 2 32 16 i/o cells 64 x 73 and logic array and logic allocator macrocells control generator 64 pt 2 pt oe 16 16 32 7 pt 7 2 32 16 i/o cells 64 x 73 and logic array and logic allocator block a/macrocells 0-15 block d/macrocells 0-15 block b/macrocells 0-15 block c/macrocells 0-15 block interconnect macrocells 64 x 73 and logic array and logic allocator control generator 64 pt 2 pt oe i/o cells 16 16 32 7 pt 7 2 32 16 macrocells 64 x 73 and logic array and logic allocator control generator 64 pt 2 pt oe i/o cells 16 16 32 7 pt 7 2 32 16 macrocells control generator 64 pt 2 pt oe 16 16 32 7 pt 7 2 32 16 i/o cells 64 x 73 and logic array and logic allocator macrocells control generator 64 pt 2 pt oe 16 16 32 7 pt 7 2 32 16 i/o cells 64 x 73 and logic array and logic allocator block a/macrocells 0-15 block d/macrocells 0-15 block b/macrocells 0-15 block c/macrocells 0-15 block interconnect s e g m e n t clk0 clk1 clk2 clk3 4 segment 0 segment 4 segment 2 segment 1 i 0 i 1 i 2 i 3 macrocells 64 x 73 and logic array and logic allocator control generator 64 pt 2 pt oe i/o cells 16 16 32 7 pt 7 2 32 16 macrocells 64 x 73 and logic array and logic allocator control generator 64 pt 2 pt oe i/o cells 16 16 32 7 pt 7 2 32 16 macrocells control generator 64 pt 2 pt oe 16 16 32 7 pt 7 2 32 16 i/o cells 64 x 73 and logic array and logic allocator macrocells control generator 64 pt 2 pt oe 16 16 32 7 pt 7 2 32 16 i/o cells 64 x 73 and logic array and logic allocator block a/macrocells 0-15 block d/macrocells 0-15 block b/macrocells 0-15 block c/macrocells 0-15 block interconnect i n t e r c o n n e c t segment 3 20446g-010
18 mach 5 family block diagram ?m5(lv)-384/xxx macrocells 64 x 73 and logic array and logic allocator control generator 64 pt 2 pt oe i/o cells 16 16 32 7 pt 7 2 32 16 macrocells 64 x 73 and logic array and logic allocator control generator 64 pt 2 pt oe i/o cells 16 16 32 7 pt 7 2 32 16 macrocells control generator 64 pt 2 pt oe 16 16 32 7 pt 7 2 32 16 i/o cells 64 x 73 and logic array and logic allocator macrocells control generator 64 pt 2 pt oe 16 16 32 7 pt 7 2 32 16 i/o cells 64 x 73 and logic array and logic allocator block a/macrocells 0-15 block d/macrocells 0-15 block b/macrocells 0-15 block c/macrocells 0-15 block interconnect macrocells 64 x 73 and logic array and logic allocator control generator 64 pt 2 pt oe i/o cells 16 16 32 7 pt 7 2 32 16 macrocells 64 x 73 and logic array and logic allocator control generator 64 pt 2 pt oe i/o cells 16 16 32 7 pt 7 2 32 16 macrocells control generator 64 pt 2 pt oe 16 16 32 7 pt 7 2 32 16 i/o cells 64 x 73 and logic array and logic allocator macrocells control generator 64 pt 2 pt oe 16 16 32 7 pt 7 2 32 16 i/o cells 64 x 73 and logic array and logic allocator block a/macrocells 0-15 block d/macrocells 0-15 block b/macrocells 0-15 block c/macrocells 0-15 block interconnect macrocells 64 x 73 and logic array and logic allocator control generator 64 pt 2 pt oe i/o cells 16 16 32 7 pt 7 2 32 16 macrocells 64 x 73 and logic array and logic allocator control generator 64 pt 2 pt oe i/o cells 16 16 32 7 pt 7 2 32 16 macrocells control generator 64 pt 2 pt oe 16 16 32 7 pt 7 2 32 16 i/o cells 64 x 73 and logic array and logic allocator macrocells control generator 64 pt 2 pt oe 16 16 32 7 pt 7 2 32 16 i/o cells 64 x 73 and logic array and logic allocator block a/macrocells 0-15 block d/macrocells 0-15 block b/macrocells 0-15 block c/macrocells 0-15 block interconnect macrocells 64 x 73 and logic array and logic allocator control generator 64 pt 2 pt oe i/o cells 16 16 32 7 pt 7 2 32 16 macrocells 64 x 73 and logic array and logic allocator control generator 64 pt 2 pt oe i/o cells 16 16 32 7 pt 7 2 32 16 macrocells control generator 64 pt 2 pt oe 16 16 32 7 pt 7 2 32 16 i/o cells 64 x 73 and logic array and logic allocator macrocells control generator 64 pt 2 pt oe 16 16 32 7 pt 7 2 32 16 i/o cells 64 x 73 and logic array and logic allocator block a/macrocells 0-15 block d/macrocells 0-15 block b/macrocells 0-15 block c/macrocells 0-15 block interconnect s e g m e n t clk0 clk1 clk2 clk3 4 segment 0 segment 5 segment 2 segment 1 i 0 i 1 i 2 macrocells 64 x 73 and logic array and logic allocator control generator 64 pt 2 pt oe i/o cells 16 16 32 7 pt 7 2 32 16 macrocells 64 x 73 and logic array and logic allocator control generator 64 pt 2 pt oe i/o cells 16 16 32 7 pt 7 2 32 16 macrocells control generator 64 pt 2 pt oe 16 16 32 7 pt 7 2 32 16 i/o cells 64 x 73 and logic array and logic allocator macrocells control generator 64 pt 2 pt oe 16 16 32 7 pt 7 2 32 16 i/o cells 64 x 73 and logic array and logic allocator block a/macrocells 0-15 block d/macrocells 0-15 block b/macrocells 0-15 block c/macrocells 0-15 block interconnect i n t e r c o n n e c t segment 3 macrocells 64 x 73 and logic array and logic allocator control generator 64 pt 2 pt oe i/o cells 16 16 32 7 pt 7 2 32 16 macrocells 64 x 73 and logic array and logic allocator control generator 64 pt 2 pt oe i/o cells 16 16 32 7 pt 7 2 32 16 macrocells control generator 64 pt 2 pt oe 16 16 32 7 pt 7 2 32 16 i/o cells 64 x 73 and logic array and logic allocator macrocells control generator 64 pt 2 pt oe 16 16 32 7 pt 7 2 32 16 i/o cells 64 x 73 and logic array and logic allocator block a/macrocells 0-15 block d/macrocells 0-15 block b/macrocells 0-15 block c/macrocells 0-15 block interconnect i 3 segment 4 20446g-011
mach 5 family 19 block diagram ?m5(lv)-512/xxx macrocells 64 x 73 and logic array and logic allocator control generator 64 pt 2 pt oe i/o cells 16 16 32 7 pt 7 2 32 16 macrocells 64 x 73 and logic array and logic allocator control generator 64 pt 2 pt oe i/o cells 16 16 32 7 pt 7 2 32 16 macrocells control generator 64 pt 2 pt oe 16 16 32 7 pt 7 2 32 16 i/o cells 64 x 73 and logic array and logic allocator macrocells control generator 64 pt 2 pt oe 16 16 32 7 pt 7 2 32 16 i/o cells 64 x 73 and logic array and logic allocator block a/macrocells 0-15 block d/macrocells 0-15 block b/macrocells 0-15 block c/macrocells 0-15 block interconnect macrocells 64 x 73 and logic array and logic allocator control generator 64 pt 2 pt oe i/o cells 16 16 32 7 pt 7 2 32 16 macrocells 64 x 73 and logic array and logic allocator control generator 64 pt 2 pt oe i/o cells 16 16 32 7 pt 7 2 32 16 macrocells control generator 64 pt 2 pt oe 16 16 32 7 pt 7 2 32 16 i/o cells 64 x 73 and logic array and logic allocator macrocells control generator 64 pt 2 pt oe 16 16 32 7 pt 7 2 32 16 i/o cells 64 x 73 and logic array and logic allocator block a/macrocells 0-15 block d/macrocells 0-15 block b/macrocells 0-15 block c/macrocells 0-15 block interconnect macrocells 64 x 73 and logic array and logic allocator control generator 64 pt 2 pt oe i/o cells 16 16 32 7 pt 7 2 32 16 macrocells 64 x 73 and logic array and logic allocator control generator 64 pt 2 pt oe i/o cells 16 16 32 7 pt 7 2 32 16 macrocells control generator 64 pt 2 pt oe 16 16 32 7 pt 7 2 32 16 i/o cells 64 x 73 and logic array and logic allocator macrocells control generator 64 pt 2 pt oe 16 16 32 7 pt 7 2 32 16 i/o cells 64 x 73 and logic array and logic allocator block a/macrocells 0-15 block d/macrocells 0-15 block b/macrocells 0-15 block c/macrocells 0-15 block interconnect macrocells 64 x 73 and logic array and logic allocator control generator 64 pt 2 pt oe i/o cells 16 16 32 7 pt 7 2 32 16 macrocells 64 x 73 and logic array and logic allocator control generator 64 pt 2 pt oe i/o cells 16 16 32 7 pt 7 2 32 16 macrocells control generator 64 pt 2 pt oe 16 16 32 7 pt 7 2 32 16 i/o cells 64 x 73 and logic array and logic allocator macrocells control generator 64 pt 2 pt oe 16 16 32 7 pt 7 2 32 16 i/o cells 64 x 73 and logic array and logic allocator block a/macrocells 0-15 block d/macrocells 0-15 block b/macrocells 0-15 block c/macrocells 0-15 block interconnect s e g m e n t clk0 clk1 clk2 clk3 4 segment 0 segment 7 segment 2 segment 1 i 0 i 1 20446g-012 continued
20 mach 5 family block diagram ?m5(lv)-512/xxx macrocells 64 x 73 and logic array and logic allocator control generator 64 pt 2 pt oe i/o cells 16 16 32 7 pt 7 2 32 16 macrocells 64 x 73 and logic array and logic allocator control generator 64 pt 2 pt oe i/o cells 16 16 32 7 pt 7 2 32 16 macrocells control generator 64 pt 2 pt oe 16 16 32 7 pt 7 2 32 16 i/o cells 64 x 73 and logic array and logic allocator macrocells control generator 64 pt 2 pt oe 16 16 32 7 pt 7 2 32 16 i/o cells 64 x 73 and logic array and logic allocator block a/macrocells 0-15 block d/macrocells 0-15 block b/macrocells 0-15 block c/macrocells 0-15 block interconnect macrocells 64 x 73 and logic array and logic allocator control generator 64 pt 2 pt oe i/o cells 16 16 32 7 pt 7 2 32 16 macrocells 64 x 73 and logic array and logic allocator control generator 64 pt 2 pt oe i/o cells 16 16 32 7 pt 7 2 32 16 macrocells control generator 64 pt 2 pt oe 16 16 32 7 pt 7 2 32 16 i/o cells 64 x 73 and logic array and logic allocator macrocells control generator 64 pt 2 pt oe 16 16 32 7 pt 7 2 32 16 i/o cells 64 x 73 and logic array and logic allocator block a/macrocells 0-15 block d/macrocells 0-15 block b/macrocells 0-15 block c/macrocells 0-15 block interconnect macrocells 64 x 73 and logic array and logic allocator control generator 64 pt 2 pt oe i/o cells 16 16 32 7 pt 7 2 32 16 macrocells 64 x 73 and logic array and logic allocator control generator 64 pt 2 pt oe i/o cells 16 16 32 7 pt 7 2 32 16 macrocells control generator 64 pt 2 pt oe 16 16 32 7 pt 7 2 32 16 i/o cells 64 x 73 and logic array and logic allocator macrocells control generator 64 pt 2 pt oe 16 16 32 7 pt 7 2 32 16 i/o cells 64 x 73 and logic array and logic allocator block a/macrocells 0-15 block d/macrocells 0-15 block b/macrocells 0-15 block c/macrocells 0-15 block interconnect macrocells 64 x 73 and logic array and logic allocator control generator 64 pt 2 pt oe i/o cells 16 16 32 7 pt 7 2 32 16 macrocells 64 x 73 and logic array and logic allocator control generator 64 pt 2 pt oe i/o cells 16 16 32 7 pt 7 2 32 16 macrocells control generator 64 pt 2 pt oe 16 16 32 7 pt 7 2 32 16 i/o cells 64 x 73 and logic array and logic allocator macrocells control generator 64 pt 2 pt oe 16 16 32 7 pt 7 2 32 16 i/o cells 64 x 73 and logic array and logic allocator block a/macrocells 0-15 block d/macrocells 0-15 block b/macrocells 0-15 block c/macrocells 0-15 block interconnect i n t e r c o n n e c t segment 6 segment 5 segment 4 segment 3 i 3 i 2 20446g-013 continued
mach 5 family 21 absolute maximum ratings m5 storage temperature . . . . . . . . . . . . . .-65 c to +150 c device junction t emperature (note 1) . . . . . . . . . . . +130 c or +150 c supply voltage with respect to ground . . . . . . . . . . . -0.5 v to +7.0 v dc input voltage . . . . . . . . . . . . . . . . . -0.5 v to 5.5 v static discharge voltage . . . . . . . . . . . . . . . . . 2000 v latchup current (-40 c to +85 c) . . . . . . . . . . 200 ma stresses above those listed under absolute maximum ratings may cause permanent device failure. functionality at or above these limits is not implied. exposure to absolute maximum ratings for extended periods may affect device r eliability. operating ranges commercial (c) devices ambient temperature (t a ) operating in free air . . . . . . . . . . . . . . . 0 c to +70 c supply voltage (v cc ) with respect to ground . . . . . . . . . +4.75 v to +5.25 v industrial (i) devices ambient temperature (t a ) operating in free air . . . . . . . . . . . . . . -40 c to +85 c supply voltage (v cc ) with respect to ground . . . . . . . . . . . +4.5 v to +5.5 v operating ranges de?e those limits between which the functionality of the device is guaranteed. note: 1. 150?for m5-128, m5-192 and m5-256 devices. 130?for m5-128/1, m5-192/1, m5-256/1, m5-320, m5-384 and m5-512 devices. 2. total i ol between ground pins should not exceed 64 ma. 3. these are absolute values with respect to device ground, and all overshoots due to system and/or tester noise are included. 4. i/o pin leakage is the worst case of i il and i ozl or i ih and i ozh . 5. not more than one output should be shorted at a time. duration of the short-circuit should not exceed one second. 5-v dc characterisitics over operating ranges parameter symbol parameter description test description min typ max unit v oh output high voltage (for m5-128/1, m5-192/1, m5-256/1, m5-320, m5-384, m5-512 devices) i oh = -3.2 ma, v cc = min, v in = v ih or v il 2.4 v i oh = -100 ?, v cc = max, v in = v ih or v il 3.3 3.6 v output high voltage (for m5-128, m5-192, m5-256 devices) i oh = -3.2 ma, v cc = min, v in = v ih or v il 2.4 v i oh = -2.5 ma, v cc = 5.25 v, v in = v ih or v il 3.6 v v ol output low voltage (note 2) i ol = +16 ma, v cc = min, v in = v ih or v il 0.5 v v ih input high voltage guaranteed input logical high voltage for all inputs (note 3) 2.0 v v il input low voltage guaranteed input logical low voltage for all inputs (note 3) 0.8 v i ih input high leakage current v in = 5.25, v cc = max (note 4) 10 a i il input low leakage current v in = 0, v cc = max (note 4) -10 a i ozh off-state output leakage current high v out = 5.25, v cc = max, v in = v ih or v il (note 4) 10 a i ozl off-state output leakage current low v out = 0, v cc = max, v in = v ih or v il (note 4) -10 a i sc output short-circuit current v out = 0.5 v cc = max, v in = v ih or v il (note 5) -30 -180 ma
22 mach 5 family absolute maximum ratings m5lv storage temperature . . . . . . . . . . . . . .-65 c to +150 c device junction temperature . . . . . . . . . . . . . +130 c supply voltage with respect to ground . . . . . . . . . . . -0.5 v to +4.5 v dc input voltage . . . . . . . . . . . . . . . . . -0.5 v to 5.5 v static discharge voltage . . . . . . . . . . . . . . . . . 2000 v latchup current (-40 c to +85 c) . . . . . . . . . . 200 ma stresses above those listed under absolute maximum ratings may cause permanent device failure. functionality at or above these limits is not implied. exposure to absolute maximum ratings for extended periods may affect device r eliability. operating ranges commercial (c) devices ambient temperature (t a ) operating in free air . . . . . . . . . . . . . . . 0 c to +70 c supply voltage (v cc ) with respect to ground . . . . . . . . . . . +3.0 v to +3.6 v industrial (i) devices ambient temperature (t a ) operating in free air . . . . . . . . . . . . . . -40 c to +85 c supply voltage (v cc ) with respect to ground . . . . . . . . . . . +3.0 v to +3.6 v operating ranges de?e those limits between which the functionality of the device is guaranteed. notes: 1. total i ol between ground pins should not exceed 64 ma. 2. these are absolute values with respect to device ground, and all overshoots due to system and/or tester noise are included. 3. i/o pin leakage is the worst case of i il and i ozl or i ih and i ozh . 4. not more than one output should be shorted at one time. duration of the short-circuit should not exceed one second. 3.3-v dc characterisitics over operating ranges parameter symbol parameter description test description min max unit v oh output high voltage v cc = min i oh = -100 a v cc -0.2 v v in = v ih or v il i oh = 3.2 ma 2.4 v v ol output low voltage v cc = min v in = v ih or v il i ol = 100 a 0.2 v i ol = 16 ma (note 1) 0.5 v v ih input high voltage v out v oh min or v out v ol max (note 2) 2.0 5.5 v v il input low voltage v out v oh min or v out v ol max (note 2) -0.3 0.8 v i ih input high leakage current v in = 3.6, v cc = max (note 3) 10 a i il input low leakage current v in = 0, v cc = max (note 3) -10 a i ozh off-state output leakage current high v out = 3.6, v cc = max, v in = v ih or v il (note 3) 10 a i ozl off-state output leakage current low v out = 0, v cc = max, v in = v ih or v il (note 3) -10 a i sc output short-circuit current v out = 0.5 v cc = max, v in = v ih or v il (note 4) -15 -160 ma
mach 5 family 23 m5(lv) timing parameters over operating ranges 1 -5 -6 -7 -10 -12 -15 -20 unit min max min max min max min max min max min max min max combinatorial delay: t pdi internal combinatorial propagation delay 3.5 4.5 5.5 8.0 10.0 13.0 18.0 ns t pd combinatorial propagation delay 5.5 6.5 7.5 10.0 12.0 15.0 20.0 ns registered delays: t ss synchronous clock setup time 3.0 3.0 4.0 5.0 6.0 8.0 10.0 ns t sa asynchronous clock setup time 3.0 3.0 4.0 5.0 6.0 7.0 8.0 ns t hs synchronous clock hold time 0.0 0.0 0.0 0.0 0.0 0.0 0.0 ns t ha asynchronous clock hold time 3.0 3.0 4.0 5.0 6.0 7.0 8.0 ns t cosi synchronous clock to internal output 2.5 3.0 4.0 5.0 6.0 8.0 10.0 ns t cos synchronous clock to output 4.5 5.0 6.0 7.0 8.0 10.0 12.0 ns t coai asynchronous clock to internal output 6.0 6.0 8.0 10.0 13.0 15.0 18.0 ns t coa asynchronous clock to output 8.0 8.0 10.0 12.0 15.0 17.0 20.0 ns latched delays: t sal latch setup time 3.0 4.0 4.0 5.0 6.0 7.0 8.0 ns t hal latch hold time 3.0 3.0 4.0 5.0 6.0 7.0 8.0 ns t pdli t ransparent latch internal 6.0 7.0 7.0 8.0 9.0 10.0 10.0 ns t pdl propagation delay through transparent latch 8.0 9.0 9.0 10.0 11.0 12.0 12.0 ns t goai gate to internal output 7.0 8.0 8.0 9.0 10.0 11.0 12.0 ns t goa gate to output 9.0 10.0 10.0 11.0 12.0 13.0 14.0 ns input register delays: t sirs input register setup time using a synchronous clock 2.0 2.0 2.0 3.0 3.0 3.0 3.0 ns t sira input register setup time using an asynchronous clock 0.0 0.0 0.0 0.0 0.0 0.0 0.0 ns t hirs input register hold time using a synchronous clock 3.0 3.0 3.0 4.0 4.0 4.0 4.0 ns t hira input register hold time using an asynchronous clock 6.0 6.0 6.0 7.0 7.0 7.0 7.0 ns input latch delays: t sil input latch setup time 2.0 2.0 2.0 3.0 3.0 3.0 3.0 ns t hil input latch hold time 6.0 6.0 6.0 7.0 7.0 7.0 7.0 ns t pdili t ransparent input latch 5.0 5.0 5.5 6.0 6.0 6.0 6.0 ns output delays: t buf output buffer delay 2.0 2.0 2.0 2.0 2.0 2.0 2.0 ns t slw slow slew rate delay 2.5 2.5 2.5 2.5 2.5 2.5 2.5 ns t ea output enable time 7.5 7.5 9.5 10.0 12.0 15.0 20.0 ns t er output disable time 7.5 7.5 9.5 10.0 12.0 15.0 20.0 ns
24 mach 5 family power delays: t pl1 power level 1 delay (note 2) 4.0 (5.0) 4.0 4.0 (5.0) 4.0 (5.0) 4.0 (5.0) 4.0 (5.0) 4.0 (5.0) ns t pl2 power level 2 delay (note 2) 6.0 (9.0) 6.0 6.0 (9.0) 6.0 (9.0) 6.0 (9.0) 6.0 (9.0) 6.0 (9.0) ns t pl3 power level 3 delay (note 2) 9.0 (17.5) 9.0 9.0 (17.5) 9.0 (17.5) 9.0 (17.5) 9.0 (17.5) 9.0 (17.5) ns additional cluster delay: t pt product term cluster delay 0.3 0.3 0.3 0.3 0.3 0.3 0.3 ns interconnect delays: t blk block interconnect delay 1.5 1.5 1.5 2.0 2.0 2.0 2.0 ns t seg segment interconnect delay 4.5 4.5 5.0 6.0 6.0 6.0 6.0 ns reset and preset delays: t sri asynchronous reset or preset to internal register output 6.0 8.0 8.0 10.0 12.0 14.0 16.0 ns t sr asynchronous reset or preset to register output 8.0 10.0 10.0 12.0 14.0 16.0 18.0 ns t srr reset and set register recovery time 5.5 7.5 7.5 8.0 9.0 10.0 11.0 ns t srw asynchronous reset or preset width 3.0 4.0 4.0 5.0 6.0 7.0 8.0 ns clock enable delays: t ces clock enable setup time 4.0 5.0 5.0 6.0 7.0 7.0 8.0 ns t ceh clock enable hold time 3.0 4.0 4.0 5.0 6.0 6.0 7.0 ns width: t wls global clock width low (note 3) 2.5 3.0 3.0 4.0 5.0 6.0 6.0 ns t whs global clock width high (note 3) 2.5 3.0 3.0 4.0 5.0 6.0 6.0 ns t wla product term clock width low 3.0 4.0 4.0 5.0 6.0 7.0 8.0 ns t wha product term clock width high 3.0 4.0 4.0 5.0 6.0 7.0 8.0 ns t gwa gate width low (for low transparent) or high (for high transparent) 3.0 4.0 4.0 5.0 6.0 7.0 8.0 ns t wir input register clock width low or high 3.0 4.0 4.0 5.0 6.0 7.0 8.0 ns m5(lv) timing parameters over operating ranges 1 (continued) -5 -6 -7 -10 -12 -15 -20 unit min max min max min max min max min max min max min max
mach 5 family 25 notes: 1. see ?ach switching test circuits?documentation on the lattice data book cd-rom or lattice web site. 2. numbers in parentheses are for m5-128, m5-192, m5-256. 3. if a signal is used as both a clock and a logic array input, then the maximum input frequency applies (f max /2). frequency: f max external feedback, pal block level. min of 1/(t wls + t whs ) or 1/(t ss + t cos ) 133 125 100 83.3 71.4 55.6 45.5 mhz internal feedback, pal block level. min of 1/(t wls + t whs ) or 1/(t ss +t cosi ) 182 167 125 100 83.3 62.5 50.0 mhz no feedback pal block level. min of 1/(t wls + t whs ) or 1/(t ss + t hs ) 200 167 167 125 100 83.3 83.3 mhz f maxa external feedback, pal block level. min of 1/(t wla + t wha ) or 1/(t sa + t coa ) 91 91 71.4 58.8 47.6 41.7 35.7 mhz internal feedback, pal block level. min of 1/(t wla + t wha ) or 1/(t sa +t coai ) 111 111 83.3 66.7 52.6 45.5 38.5 mhz no feedback, pal block level. min of 1/(t wla + t wha ) or 1/(t sa + t ha ) 167 125 125 100 83.3 71.4 62.5 mhz f maxi maximum input register frequency 1/(t sirs +t hirs ) or 1/(2 x t wicw ) 167 125 125 100 83.3 71.4 62.5 mhz m5(lv) timing parameters over operating ranges 1 (continued) -5 -6 -7 -10 -12 -15 -20 unit min max min max min max min max min max min max min max
26 mach 5 family 1. these parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modi?d wh ere these parameters may be affected. i cc vs. frequency these curves represent the typical power consumption for a particular device at system frequency. the selected ?ypical?pattern is a 16-bit up-down counter. this pattern ?ls the device and exercises every macrocell. maximum frequency shown uses internal feedback and a d-type register. power/speed are optimized to obtain the highest counter frequency and the lowest power. the highest frequency (lsbs) is placed in common pal blocks, which are set to high power. the lowest frequency signals (msbs) are placed in a common pal block and set to lowest power. for a more detailed discussion about mach 5 power consumption, refer to the application note entitled mach 5 power in the application notes section on the lattice data book cd-rom or lattice web site. i cc curves at high /low power modes capacitance 1 parameter symbol parameter description test conditions typ unit c in i/clk pin v in =2.0 v 3.3 v or 5 v, 25?c, 1 mhz 12 pf c i/o i/o pin v out =2.0 v 3.3 v or 5 v, 25?c, 1 mhz 10 pf 700 600 500 400 300 200 100 0 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 v cc = 5 v or 3.3 v, t a = 25?c m5(lv)-512 high power m5(lv)-384 high power m5(lv)-320 high power m5-256/1 and m5lv-25 high power m5-128/1 and m5lv-128 high power m5(lv)-384 low power m5(lv)-320 low power m5-256/1 and m5lv-256 low power m5-128/1 and m5lv-128 low power i cc (ma) frequency (mhz) 20446g-048 figure 8. i cc curves at high/low power modes m5-192/1 high power m5-192/1 low power m5(lv)-512 low power
mach 5 family 27 700 600 500 400 300 200 100 0 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 v cc = 5 v, t a = 25?c m5-256 high power m5-256 low power i cc (ma) frequency (mhz) m5-192 high power m5-128 high power m5-192 low power m5-128 low power 20446g-049 figure 9. i cc curves at high/low power modes
28 mach 5 family 100-pin pqfp connection diagram t op view 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 gnd gnd tdi i/o0 i/o1 i/o2 i/o3 i/o4 i/o5 i/o6 i/o7 i/o8 i0/clk0 v cc v cc gnd gnd i1/clk1 i/o9 i/o10 i/o11 i/o12 i/o13 i/o14 i/o15 i/o16 i/o17 tck gnd gnd m5-128 m5lv-128* m5-128 m5lv-128* m5-192* m5-256* m5lv-256 m5-256* m5lv-256 m5-256* m5lv-256 m5-256* m5lv-256 m5-192* m5-192* m5-192* m5-128 m5lv-128* *package obsolete, contact factory. m5-128 m5lv-128* 0a12 0b13 0b12 0b11 0b8 0b7 0b4 0b3 0b2 1b2 1b3 1b4 1b7 1b8 1b11 1b12 1b13 1a12 0a12 0b13 0b12 0b11 0b8 0b7 0b4 0b3 0b2 1b2 1b3 1b4 1b7 1b8 1b11 1b12 1b13 1a12 0a14 0b13 0b12 0b11 0b8 0b7 0b4 0b3 0b2 1b2 1b3 1b4 1b7 1b8 1b11 1b12 1b13 1a14 3a12 3b13 3b12 3b11 3b8 3b7 3b4 3b3 3b2 2b2 2b3 2b4 2b7 2b8 2b11 2b12 2b13 2a12 2a12 2b13 2b12 2b11 2b8 2b7 2b4 2b3 2b2 2c2 2c3 2c4 2c7 2c8 2c11 2c12 2c13 2d12 0d14 0c13 0c12 0c11 0c8 0c7 0c4 0c3 0c2 1c2 1c3 1c4 1c7 1c8 1c11 1c12 1c13 1d14 gnd gnd tdo i/o51 i/o50 i/o49 i/o48 i/o47 i/o46 i/o45 i/o44 i/o43 i3/clk3 gnd gnd v cc v cc i2/clk2 i/o42 i/o41 i/o40 i/o39 i/o38 i/o37 i/o36 i/o35 i/o34 tms gnd gnd 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 i/o18 i/o19 i/o20 i/o21 i/o22 i/o23 i/o24 i/o25 v cc gnd gnd v cc i/o26 i/o27 i/o28 i/o29 i/o30 i/o31 i/o32 i/o33 1a7 1a6 1a5 1a4 1a3 1a2 1a1 1a0 2a0 2a1 2a2 2a3 2a4 2a5 2a6 2a7 1a7 1a6 1a5 1a4 1a3 1a2 1a1 1a0 2d0 2d1 2d2 2d3 2d4 2d5 2d6 2d7 1a13 1a12 1a11 1a8 1a7 1a4 1a3 1a2 1d2 1d3 1d4 1d7 1d8 1d11 1d12 1d13 0a7 0a6 0a5 0a4 0a3 0a2 0a1 0a0 3a0 3a1 3a2 3a3 3a4 3a5 3a6 3a7 0a7 0a6 0a5 0a4 0a3 0a2 0a1 0a0 2a0 2a1 2a2 2a3 2a4 2a5 2a6 2a7 0d2 0d3 0d4 0d7 0d8 0d11 0d12 0d13 0a13 0a12 0a11 0a8 0a7 0a4 0a3 0a2 i/o67 i/o66 i/o65 i/o64 i/o63 i/o62 i/o61 i/o60 v cc gnd gnd v cc i/o59 i/o58 i/o57 i/o56 i/o55 i/o54 i/o53 i/o52 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 20446g-016 100-pin pqfp (68 i/o) 3d15 clk = clock gnd = ground i= input i/o = input/output nc = no connect v cc = supply voltage tdi = test data in tck = test clock tms = test mode select tdo = test data out pin designations macrocell (0-15) p al block (a-d) segment (0-3)
mach 5 family 29 100-pin tqfp connection diagram ?68 i/o t op view 100-pin tqfp (68 i/o) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 tdi i/o0 i/o1 i/o2 i/o3 i/o4 i/o5 i/o6 i/o7 i/o8 i0/clk0 v cc gnd gnd i1/clk1 i/o9 i/o10 i/o11 i/o12 i/o13 i/o14 i/o15 i/o16 i/o17 tck gnd gnd i/o18 i/o19 i/o20 i/o21 i/o22 i/o23 i/o24 i/o25 nc v cc gnd gnd v cc i/o26 i/o27 i/o28 i/o29 i/o30 i/o31 i/o32 i/o33 gnd gnd gnd gnd nc i/o67 i/o66 i/o65 i/o64 i/o63 i/o62 i/o61 i/o60 v cc gnd gnd v cc nc i/o59 i/o58 i/o57 i/o56 i/o55 i/o54 i/o53 i/o52 gnd 0a7 0a6 0a5 0a4 0a3 0a2 0a1 0a0 3a0 3a1 3a2 3a3 3a4 3a5 3a6 3a7 0a7 0a6 0a5 0a4 0a3 0a2 0a1 0a0 2a0 2a1 2a2 2a3 2a4 2a5 2a6 2a7 0a13 0a12 0a11 0a8 0a7 0a4 0a3 0a2 0d2 0d3 0d4 0d7 0d8 0d11 0d12 0d13 1a7 1a6 1a5 1a4 1a3 1a2 1a1 1a0 2a0 2a1 2a2 2a3 2a4 2a5 2a6 2a7 1a7 1a6 1a5 1a4 1a3 1a2 1a1 1a0 2d0 2d1 2d2 2d3 2d4 2d5 2d6 2d7 1a13 1a12 1a11 1a8 1a7 1a4 1a3 1a2 1d2 1d3 1d4 1d7 1d8 1d11 1d12 1d13 gnd tdo i/o51 i/o50 i/o49 i/o48 i/o47 i/o46 i/o45 i/o44 i/o43 i3/clk3 gnd v cc i2/clk2 i/o42 i/o41 i/o40 i/o39 i/o38 i/o37 i/o36 i/o35 i/o34 tms 3a12 3b13 3b12 3b11 3b8 3b7 3b4 3b3 3b2 m5-128 m5lv-128 m5-128 m5lv-128 m5-128 m5lv-128 m5-192 m5-256 m5lv-256* m5-256 m5lv-256* m5-256 m5lv-256* m5-256 m5lv-256* m5-192 m5-192 m5-192 m5-128 m5lv-128 2b2 2b3 2b4 2b7 2b8 2b11 2b12 2b13 2a12 2a12 2b13 2b12 2b11 2b8 2b7 2b4 2b3 2b2 2c2 2c3 2c4 2c7 2c8 2c11 2c12 2c13 2d12 0d14 0c13 0c12 0c11 0c8 0c7 0c4 0c3 0c2 1c2 1c3 1c4 1c7 1c8 1c11 1c12 1c13 1d14 0a12 0b13 0b12 0b11 0b8 0b7 0b4 0b3 0b2 1b2 1b3 1b4 1b7 1b8 1b11 1b12 1b13 1a12 0a12 0b13 0b12 0b11 0b8 0b7 0b4 0b3 0b2 1b2 1b3 1b4 1b7 1b8 1b11 1b12 1b13 1a12 0a14 0b13 0b12 0b11 0b8 0b7 0b4 0b3 0b2 1b2 1b3 1b4 1b7 1b8 1b11 1b12 1b13 1a14 *package obsolete, contact factory. 20446g-017 3d15 clk = clock gnd = ground i= input i/o = input/output nc = no connect v cc = supply voltage tdi = test data in tck = test clock tms = test mode select tdo = test data out pin designations macrocell (0-15) p al block (a-d) segment (0-3)
30 mach 5 family 100-pin tqfp connection diagram ?74 i/o t op view 100-pin tqfp (74 i/o) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 tdi i/o0 i/o1 i/o2 i/o3 i/o4 i/o5 i/o6 i/o7 i/o8 i0/clk0 v cc gnd gnd i1/clk1 i/o9 i/o10 i/o11 i/o12 i/o13 i/o14 i/o15 i/o16 i/o17 tck gnd i/o18 i/o19 i/o20 i/o21 i/o22 i/o23 i/o24 i/o25 i/o26 1/o27 v cc gnd gnd v cc i/o28 i/o29 i/o30 i/o31 i/o32 i/o33 i/o34 i/o35 1/o36 gnd gnd i/o73 i/o72 i/o71 i/o70 i/o69 i/o68 i/o67 i/o66 i/o65 i/o64 v cc gnd gnd v cc i/o63 i/o62 i/o61 i/o60 i/o59 i/o58 i/o57 i/o56 i/o55 gnd 0a7 0a6 0a5 0a4 0a3 0a2 0a1 0a0 0d11 0d12 3d12 3a0 3a1 3a2 3a3 3a4 3a5 3a6 3a7 1a7 1a6 1a5 1a4 1a3 1a2 1a1 1a0 1d11 1d12 2d12 2a0 2a1 2a2 2a3 2a4 2a5 2a6 2a7 0a13 0a12 0a11 0a10 0a9 0a8 0a7 0a4 0a3 0a2 0d1 0d2 0d3 0d4 0d7 0d8 0d11 0d12 0d13 1a13 1a12 1a11 1a10 1a8 1a7 1a4 1a3 1a2 1a1 1d2 1d3 1d4 1d7 1d8 1d10 1d11 1d12 1d13 gnd tdo i/o54 i/o53 i/o52 i/o51 i/o50 i/o49 i/o48 i/o47 i/o46 i3/clk3 gnd v cc i2/clk2 i/o45 i/o44 i/o43 i/o42 i/o41 i/o40 i/o39 i/o38 i/o37 tms 3a12 3b13 3b12 3b11 3b8 3b7 3b4 3b3 3b2 m5lv-256 m5lv-128 m5lv-128 m5lv-128 m5lv-128 m5lv-256 m5lv-256 m5lv-256 2b2 2b3 2b4 2b7 2b8 2b11 2b12 2b13 2a12 0d14 0c13 0c12 0c11 0c8 0c7 0c4 0c3 0c2 1c2 1c3 1c4 1c7 1c8 1c11 1c12 1c13 1d14 0a12 0b13 0b12 0b11 0b8 0b7 0b4 0b3 0b2 1b2 1b3 1b4 1b7 1b8 1b11 1b12 1b13 1a12 0a14 0b13 0b12 0b11 0b8 0b7 0b4 0b3 0b2 1b2 1b3 1b4 1b7 1b8 1b11 1b12 1b13 1a14 20446g-018 3d15 clk = clock gnd = ground i= input i/o = input/output nc = no connect v cc = supply voltage tdi = test data in tck = test clock tms = test mode select tdo = test data out pin designations macrocell (0-15) p al block (a-d) segment (0-3)
mach 5 family 31 144-pin pqfp connection diagram t op view 144-pin pqfp 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 tdi i/o0 i/o1 i/o2 i/o3 i/o4 gnd i/o5 i/o6 i/o7 i/o8 gnd i/o9 i/o10 i/o11 i/o12 i0/clk0 v cc gnd i1/clk1 i/o13 i/o14 i/o15 i/o16 gnd i/o17 i/o18 i/o19 i/o20 gnd i/o21 i/o22 i/o23 i/o24 i/o25 tck 0a8 0a9 0a10 0a11 0a12 0b13 0b12 0b11 0b8 0b5 0b4 0b3 0b2 1b2 1b3 1b4 1b5 1b8 1b11 1b12 1b13 1a12 1a11 1a10 1a9 1a8 0a12 0a13 0a14 0b13 0b12 0b11 0b8 0b5 0b4 0b3 0b2 0b1 0b0 1b0 1b1 1b2 1b3 1b4 1b5 1b8 1b11 1b12 1b13 1a14 1a13 1a12 0a14 0b13 0b12 0b11 0b10 0b8 0b7 0b6 0b5 0b4 0b3 0b2 0b1 1b1 1b2 1b3 1b4 1b5 1b6 1b7 1b8 1b10 1b11 1b12 1b13 1a14 m5-128 m5lv-128* m5-256* m5lv-256* m5-256* m5lv-256* m5-256* m5lv-256* m5-256* m5lv-256* m5-192* m5-192* m5-192* m5-192* m5-128 m5lv-128* m5-128 m5lv-128* m5-128 m5lv-128* 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 gnd v cc i/o26 i/o27 i/o28 i/o29 i/o30 i/o31 i/o32 gnd i/o33 i/o34 i/o35 i/o36 i/o37 i/o38 v cc gnd gnd v cc i/o39 i/o40 i/o41 i/o42 i/o43 i/o44 gnd i/o45 i/o46 i/o47 i/o48 i/o49 i/o50 i/o51 v cc gnd 1a7 1a6 1a5 1a4 1a3 1a2 1a1 1d3 1d4 1d7 1d8 1d11 1d12 2d12 2d11 2d8 2d7 2d4 2d3 2a1 2a2 2a3 2a4 2a5 2a6 2a7 1a11 1a10 1a8 1a7 1a6 1a5 1a4 1a3 1a2 1d2 1d3 1d4 1d7 1d8 1d11 1d12 1d13 2d2 2d3 2d4 2d5 2d6 2d7 2d8 2d10 2d11 1a13 1a12 1a11 1a10 1a8 1a7 1a6 1a5 1a4 1a3 1a2 1a1 1a0 1d0 1d1 1d2 1d3 1d4 1d5 1d6 1d7 1d8 1d10 1d11 1d12 1d13 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 gnd v cc i/o103 i/o102 i/o101 i/o100 i/o99 i/o98 i/o97 gnd i/o96 i/o95 i/o94 i/o93 i/o92 i/o91 v cc gnd gnd v cc i/o90 i/o89 i/o88 i/o87 i/o86 i/o85 gnd i/o84 i/o83 i/o82 i/o81 i/o80 i/o79 i/o78 v cc gnd 0a7 0a6 0a5 0a4 0a3 0a2 0a1 0d3 0d4 0d7 0d8 0d11 0d12 3d12 3d11 3d8 3d7 3d4 3d3 3a1 3a2 3a3 3a4 3a5 3a6 3a7 0a11 0a10 0a8 0a7 0a6 0a5 0a4 0a3 0a2 0d2 0d3 0d4 0d7 0d8 0d11 0d12 0d13 2a2 2a3 2a4 2a5 2a6 2a7 2a8 2a10 2a11 0a13 0a12 0a11 a10 0a8 0a7 0a6 0a5 0a4 0a3 0a2 0a1 0a0 0d0 0d1 0d2 0d3 0d4 0d5 0d6 0d7 0d8 0d10 0d11 0d12 0d13 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 tdo i/o77 i/o76 i/o75 i/o74 i/o73 gnd i/o72 i/o71 i/o70 i/o69 gnd i/o68 i/o67 i/o66 i/o65 i3/clk3 gnd v cc i2/clk2 i/o64 i/o63 i/o62 i/o61 gnd i/o60 i/o59 i/o58 i/o57 gnd i/o56 i/o55 i/o54 i/o53 i/o52 tms 3a8 3a9 3a10 3a11 3a12 3b13 3b12 3b11 3b8 3b5 3b4 3b3 3b2 2b2 2b3 2b4 2b5 2b8 2b11 2b12 2b13 2a12 2a11 2a10 2a9 2a8 2a12 2a13 2a14 2b13 2b12 2b11 2b8 2b5 2b4 2b3 2b2 2b1 2b0 2c0 2c1 2c2 2c3 2c4 2c5 2c8 2c11 2c12 2c13 2d14 2d13 2d12 0d14 0c13 0c12 0c11 0c10 0c8 0c7 0c6 0c5 0c4 0c3 0c2 0c1 1c1 1c2 1c3 1c4 1c5 1c6 1c7 1c8 1c10 1c11 1c12 1c13 1d14 *package obsolete, contact factory. 20446g-019 3d15 clk = clock gnd = ground i= input i/o = input/output nc = no connect v cc = supply voltage tdi = test data in tck = test clock tms = test mode select tdo = test data out pin designations macrocell (0-15) p al block (a-d) segment (0-3)
32 mach 5 family 144-pin tqfp connection diagram t op view 144-pin tqfp 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 tdi i/o0 i/o1 i/o2 i/o3 i/o4 gnd i/o5 i/o6 i/o7 i/o8 gnd i/o9 i/o10 i/o11 i/o12 i0/clk0 v cc gnd i1/clk1 i/o13 i/o14 i/o15 i/o16 gnd i/o17 i/o18 i/o19 i/o20 gnd i/o21 i/o22 i/o23 i/o24 i/o25 tck 0a8 0a9 0a10 0a11 0a12 0b13 0b12 0b11 0b8 0b5 0b4 0b3 0b2 1b2 1b3 1b4 1b5 1b8 1b11 1b12 1b13 1a12 1a11 1a10 1a9 1a8 0a14 0b13 0b12 0b11 0b10 0b8 0b7 0b6 0b5 0b4 0b3 0b2 0b1 1b1 1b2 1b3 1b4 1b5 1b6 1b7 1b8 1b10 1b11 1b12 1b13 1a14 m5lv-128 m5lv-256 m5lv-256 m5lv-256 m5lv-256 m5lv-128 m5lv-128 m5lv-128 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 gnd v cc i/o26 i/o27 i/o28 i/o29 i/o30 i/o31 i/o32 gnd i/o33 i/o34 i/o35 i/o36 i/o37 i/o38 v cc gnd gnd v cc i/o39 i/o40 i/o41 i/o42 i/o43 i/o44 gnd i/o45 i/o46 i/o47 i/o48 i/o49 i/o50 i/o51 v cc gnd 1a7 1a6 1a5 1a4 1a3 1a2 1a1 1d3 1d4 1d7 1d8 1d11 1d12 2d12 2d11 2d8 2d7 2d4 2d3 2a1 2a2 2a3 2a4 2a5 2a6 2a7 1a13 1a12 1a11 1a10 1a8 1a7 1a6 1a5 1a4 1a3 1a2 1a1 1a0 1d0 1d1 1d2 1d3 1d4 1d5 1d6 1d7 1d8 1d10 1d11 1d12 1d13 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 gnd v cc i/o103 i/o102 i/o101 i/o100 i/o99 i/o98 i/o97 gnd i/o96 i/o95 i/o94 i/o93 i/o92 i/o91 v cc gnd gnd v cc i/o90 i/o89 i/o88 i/o87 i/o86 i/o85 gnd i/o84 i/o83 i/o82 i/o81 i/o80 i/o79 i/o78 v cc gnd 0a7 0a6 0a5 0a4 0a3 0a2 0a1 0d3 0d4 0d7 0d8 0d11 0d12 3d12 3d11 3d8 3d7 3d4 3d3 3a1 3a2 3a3 3a4 3a5 3a6 3a7 0a13 0a12 0a11 a10 0a8 0a7 0a6 0a5 0a4 0a3 0a2 0a1 0a0 0d0 0d1 0d2 0d3 0d4 0d5 0d6 0d7 0d8 0d10 0d11 0d12 0d13 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 tdo i/o77 i/o76 i/o75 i/o74 i/o73 gnd i/o72 i/o71 i/o70 i/o69 gnd i/o68 i/o67 i/o66 i/o65 i3/clk3 gnd v cc i2/clk2 i/o64 i/o63 i/o62 i/o61 gnd i/o60 i/o59 i/o58 i/o57 gnd i/o56 i/o55 i/o54 i/o53 i/o52 tms 3a8 3a9 3a10 3a11 3a12 3b13 3b12 3b11 3b8 3b5 3b4 3b3 3b2 2b2 2b3 2b4 2b5 2b8 2b11 2b12 2b13 2a12 2a11 2a10 2a9 2a8 0d14 0c13 0c12 0c11 0c10 0c8 0c7 0c6 0c5 0c4 0c3 0c2 0c1 1c1 1c2 1c3 1c4 1c5 1c6 1c7 1c8 1c10 1c11 1c12 1c13 1d14 20446g-020 3d15 clk = clock gnd = ground i= input i/o = input/output nc = no connect v cc = supply voltage tdi = test data in tck = test clock tms = test mode select tdo = test data out pin designations macrocell (0-15) p al block (a-d) segment (0-3)
mach 5 family 33 160-pin pqfp connection diagram t op view 160-pin pqfp (128, 192, 256 macrocells) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 tdi i/o0 i/o1 i/o2 i/o3 i/o4 i/o5 i/o6 i/o7 gnd i/o8 i/o9 i/o10 i/o11 i/o12 i/o13 i/o14 i/o15 i0/clk0 v cc gnd i1/clk1 i/o16 i/o17 i/o18 i/o19 i/o20 i/o21 i/o22 i/o23 gnd i/o24 i/o25 i/o26 i/o27 i/o28 i/o29 i/o30 i/o31 tck 0a8 0a9 0a10 0a11 0a12 0a13 0a14 0a15 0b13 0b12 0b11 0b8 0b5 0b4 0b3 0b2 1b2 1b3 1b4 1b5 1b8 1b11 1b12 1b13 1a15 1a14 1a13 1a12 1a11 1a10 1a9 1a8 0a12 0a13 0a14 0a15 0b15 0b14 0b13 0b12 0b11 0b8 0b5 0b4 0b3 0b2 0b1 0b0 1b0 1b1 1b2 1b3 1b4 1b5 1b8 1b11 1b12 1b13 1b14 1b15 1a15 1a14 1a13 1a12 0a14 0a15 0b14 0b13 0b12 0b11 0b10 0b9 0b8 0b7 0b6 0b5 0b4 0b3 0b2 0b1 1b1 1b2 1b3 1b4 1b5 1b6 1b7 1b8 1b9 1b10 1b11 1b12 1b13 1b14 1a15 1a14 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 gnd v cc i/o32 i/o33 i/o34 i/o35 i/o36 i/o37 i/o38 i/o39 gnd v cc i/o40 i/o41 i/o42 i/o43 i/o44 i/o45 v cc gnd gnd v cc i/o46 i/o47 i/o48 i/o49 i/o50 i/o51 v cc gnd i/o52 i/o53 i/o54 i/o55 i/o56 i/o57 i/o58 i/o59 v cc gnd 1a7 1a6 1a5 1a4 1a3 1a2 1a1 1a0 1d3 1d4 1d7 1d8 1d11 1d12 2d12 2d11 2d8 2d7 2d4 2d3 2a0 2a1 2a2 2a3 2a4 2a5 2a6 2a7 1a11 1a10 1a9 1a8 1a7 1a6 1a5 1a4 1a3 1a2 1d2 1d3 1d4 1d7 1d8 1d11 1d12 1d13 2d2 2d3 2d4 2d5 2d6 2d7 2d8 2d9 2d10 2d11 1a13 1a12 1a11 1a10 1a9 1a8 1a7 1a6 1a5 1a4 1a3 1a2 1a1 1a0 1d0 1d1 1d2 1d3 1d4 1d5 1d6 1d7 1d8 1d9 1d10 1d11 1d12 1d13 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 gnd v cc i/o119 i/o118 i/o117 i/o116 i/o115 i/o114 i/o113 i/o112 gnd v cc i/o111 i/o110 i/o109 i/o108 i/o107 i/o106 v cc gnd gnd v cc i/o105 i/o104 i/o103 i/o102 i/o101 i/o100 v cc gnd i/o99 i/o98 i/o97 i/o96 i/o95 i/o94 i/o93 i/o92 v cc gnd 0a7 0a6 0a5 0a4 0a3 0a2 0a1 0a0 0d3 0d4 0d7 0d8 0d11 0d12 3d12 3d11 3d8 3d7 3d4 3d3 3a0 3a1 3a2 3a3 3a4 3a5 3a6 3a7 0a11 0a10 0a9 0a8 0a7 0a6 0a5 0a4 0a3 0a2 0d2 0d3 0d4 0d7 0d8 0d11 0d12 0d13 2a2 2a3 2a4 2a5 2a6 2a7 2a8 2a9 2a10 2a11 0a13 0a12 0a11 0a10 0a9 0a8 0a7 0a6 0a5 0a4 0a3 0a2 0a1 0a0 0d0 0d1 0d2 0d3 0d4 0d5 0d6 0d7 0d8 0d9 0d10 0d11 0d12 0d13 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 tdo i/o91 i/o90 i/o89 i/o88 i/o87 i/o86 i/o85 i/o84 gnd i/o83 i/o82 i/o81 i/o80 i/o79 i/o78 i/o77 i/o76 i3/clk3 gnd v cc i2/clk2 i/o75 i/o74 i/o73 i/o72 i/o71 i/o70 i/o69 i/o68 gnd i/o67 i/o66 i/o65 i/o64 i/o63 i/o62 i/o61 i/o60 tms 3a8 3a9 3a10 3a11 3a12 3a13 3a14 3a15 3b13 3b12 3b11 3b8 3b5 3b4 3b3 3b2 2b2 2b3 2b4 2b5 2b8 2b11 2b12 2b13 2a15 2a14 2a13 2a12 2a11 2a10 2a9 2a8 m5-128 m5lv-128 m5-128 m5lv-128 m5-128 m5lv-128 m5-256 m5lv-256 m5-256 m5lv-256 m5-256 m5lv-256 m5-256 m5lv-256 m5-192 m5-192 m5-192 m5-192 m5-128 m5lv-128 2a12 2a13 2a14 2a15 2b15 2b14 2b13 2b12 2b11 2b8 2b5 2b4 2b3 2b2 2b1 2b0 2c0 2c1 2c2 2c3 2c4 2c5 2c8 2c11 2c12 2c13 2c14 2c15 2d15 2d14 2d13 2d12 0d14 0d15 0c14 0c13 0c12 0c11 0c10 0c9 0c8 0c7 0c6 0c5 0c4 0c3 0c2 0c1 1c1 1c2 1c3 1c4 1c5 1c6 1c7 1c8 1c9 1c10 1c11 1c12 1c13 1c14 1d15 1d14 20446g-021 3d15 clk = clock gnd = ground i= input i/o = input/output nc = no connect v cc = supply voltage tdi = test data in tck = test clock tms = test mode select tdo = test data out pin designations macrocell (0-15) p al block (a-d) segment (0-3)
34 mach 5 family 160-pin pqfp (with internal heat spreader) connection diagram t op view 160-pin pqfp (320, 384, 512 macrocells) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 tdi i/o0 i/o1 i/o2 i/o3 i/o4 i/o5 i/o6 i/o7 gnd i/o8 i/o9 i/o10 i/o11 i/o12 i/o13 i/o14 i/o15 i0/clk0 v cc gnd i1/clk1 i/o16 i/o17 i/o18 i/o19 i/o20 i/o21 i/o22 i/o23 gnd i/o24 i/o25 i/o26 i/o27 i/o28 i/o29 i/o30 i/o31 tck 0a2 0a3 0a4 0a7 0a8 0a11 0a12 0a13 0d13 0d12 0d11 0d8 0d7 0d4 0d3 0d2 1d2 1d3 1d4 1d7 1d8 1d11 1d12 1d13 1a13 1a12 1a11 1a8 1a7 1a4 1a3 1a2 0a2 0a3 0a4 0a7 0a8 0a11 0a12 0a13 0d13 0d12 0d11 0d8 0d7 0d4 0d3 0d2 1d2 1d3 1d4 1d7 1d8 1d11 1d12 1d13 1a13 1a12 1a11 1a8 1a7 1a4 1a3 1a2 0a2 0a3 0a4 0a7 0a8 0a11 0a12 0a13 0d13 0d12 0d11 0d8 0d7 0d4 0d3 0d2 1d2 1d3 1d4 1d7 1d8 1d11 1d12 1d13 1a15 1a14 1a13 1a12 1a11 1a10 1a9 1a8 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 gnd v cc i/o32 i/o33 i/o34 i/o35 i/o36 i/o37 i/o38 i/o39 gnd v cc i/o40 i/o41 i/o42 i/o43 i/o44 i/o45 v cc gnd gnd v cc i/o46 i/o47 i/o48 i/o49 i/o50 i/o51 v cc gnd i/o52 i/o53 i/o54 i/o55 i/o56 i/o57 i/o58 i/o59 v cc gnd 2a13 2a12 2a11 2a8 2a7 2a4 2a3 2a2 2b3 2b4 2b7 2b8 2b11 2b12 3b12 3b11 3b8 3b7 3b4 3b3 3a2 3a3 3a4 3a7 3a8 3a11 3a12 3a13 1b2 1b3 1b4 1b7 1b8 1b11 1b12 1b13 2a12 2a11 2a8 2a7 2a4 2a3 2b3 2b4 2b7 2b8 2b11 2b12 3b13 3b12 3b11 3b8 3b7 3b4 3b3 3b2 1a7 1a6 1a5 1a4 1a3 1a2 1a1 1a0 1b3 1b4 1b7 1b8 1b11 1b12 2b12 2b11 2b8 2b7 2b4 2b3 2a0 2a1 2a2 2a3 2a4 2a5 2a6 2a7 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 gnd v cc i/o119 i/o118 i/o117 i/o116 i/o115 i/o114 i/o113 i/o112 gnd v cc i/o111 i/o110 i/o109 i/o108 i/o107 i/o106 v cc gnd gnd v cc i/o105 i/o104 i/o103 i/o102 i/o101 i/o100 v cc gnd i/o99 i/o98 i/o97 i/o96 i/o95 i/o94 i/o93 i/o92 v cc gnd 7a13 7a12 7a11 7a8 7a7 7a4 7a3 7a2 7b3 7b4 7b7 7b8 7b11 7b12 6b12 6b11 6b8 6b7 6b4 6b3 6a2 6a3 6a4 6a7 6a8 6a11 6a12 6a13 0b2 0b3 0b4 0b7 0b8 0b11 0b12 0b13 5a12 5a11 5a8 5a7 5a4 5a3 5b3 5b4 5b7 5b8 5b11 5b12 4b13 4b12 4b11 4b8 4b7 4b4 4b3 4b2 0b2 0b3 0b4 0b7 0b8 0b11 0b12 0b13 4a12 4a11 4a8 4a7 4a4 4a3 4b3 4b4 4b7 4b8 4b11 4b12 3b13 3b12 3b11 3b8 3b7 3b4 3b3 3b2 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 tdo i/o91 i/o90 i/o89 i/o88 i/o87 i/o86 i/o85 i/o84 gnd i/o83 i/o82 i/o81 i/o80 i/o79 i/o78 i/o77 i/o76 i3/clk3 gnd v cc i2/clk2 i/o75 i/o74 i/o73 i/o72 i/o71 i/o70 i/o69 i/o68 gnd i/o67 i/o66 i/o65 i/o64 i/o63 i/o62 i/o61 i/o60 tms 5a2 5a3 5a4 5a7 5a8 5a11 5a12 5a13 5d13 5d12 5d11 5d8 5d7 5d4 5d3 5d2 4d2 4d3 4d4 4d7 4d8 4d11 4d12 4d13 4a13 4a12 4a11 4a8 4a7 4a4 4a3 4a2 m5-320* m5lv-320 m5-384* m5lv-384 m5-384* m5lv-384 m5-384* m5lv-384 m5-384* m5lv-384 m5-512* m5lv-512 m5-512* m5lv-512 m5-512* m5lv-512 m5-512* m5lv-512 m5-320* m5lv-320 m5-320* m5lv-320 m5-320* m5lv-320 4a2 4a3 4a4 4a7 4a8 4a11 4a12 4a13 4d13 4d12 4d11 4d8 4d7 4d4 4d3 4d2 3d2 3d3 3d4 3d7 3d8 3d11 3d12 3d13 3a13 3a12 3a11 3a8 3a7 3a4 3a3 3a2 3a2 3a3 3a4 3a7 3a8 3a11 3a12 3a13 3d13 3d12 3d11 3d8 3d7 3d4 3d3 3d2 2d2 2d3 2d4 2d7 2d8 2d11 2d12 2d13 2a15 2a14 2a13 2a12 2a11 2a10 2a9 2a8 *package obsolete, contact factory. 20446g-022 7d15 clk = clock gnd = ground i= input i/o = input/output nc = no connect v cc = supply voltage tdi = test data in tck = test clock tms = test mode select tdo = test data out pin designations macrocell (0-15) p al block (a-d) segment (0-7)
mach 5 family 35 208-pin pqfp connection diagram t op view 208-pin pqfp (256 macrocells) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 tdi i/o0 i/o1 i/o2 i/o3 i/o4 i/o5 i/o6 i/o7 v cc gnd i/o8 i/o9 i/o10 i/o11 i/o12 i/o13 i/o14 i/o15 gnd i/o16 i/o17 i/o18 i/o19 i0/clk0 v cc gnd i1/clk1 i/o20 i/o21 i/o22 i/o23 gnd i/o24 i/o25 i/o26 i/o27 i/o28 i/o29 i/o30 i/o31 gnd v cc i/o32 i/o33 i/o34 i/o35 i/o36 i/o37 i/o38 i/o39 tck 0a8 0a9 0a10 0a11 0a12 0a13 0a14 0a15 0b13 0b12 0b11 0b10 0b9 0b8 0b7 0b6 0b5 0b4 0b3 0b2 1b2 1b3 1b4 1b5 1b6 1b7 1b8 1b9 1b10 1b11 1b12 1b13 1a15 1a14 1a13 1a12 1a11 1a10 1a9 1a8 tdo i/o119 i/o118 i/o117 i/o116 i/o115 i/o114 i/o113 i/o112 v cc gnd i/o111 i/o110 i/o109 i/o108 i/o107 i/o106 i/o105 i/o104 gnd i/o103 i/o102 i/o101 i/o100 i3/clk3 gnd v cc i2/clk2 i/o99 i/o98 i/o97 i/o96 gnd i/o95 i/o94 i/o93 i/o92 i/o91 i/o90 i/o89 i/o88 gnd v cc i/o87 i/o86 i/o85 i/o84 i/o83 i/o82 i/o81 i/o80 tms 3a8 3a9 3a10 3a11 2a12 3a13 3a14 3a15 3b13 3b12 3b11 3b10 3b9 3b8 3b7 3b6 3b5 3b4 3b3 3b2 2b2 2b3 2b4 2b5 2b6 2b7 2b8 2b9 2b10 2b11 2b12 2b13 2a15 2a14 2a13 2a12 2a11 2a10 2a9 2a8 m5-256 m5lv-256 m5-256 m5lv-256 m5-256 m5lv-256 m5-256 m5lv-256 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 gnd i/o40 i/o41 i/o42 i/o43 i/o44 i/o45 i/o46 i/o47 gnd v cc i/o48 i/o49 i/o50 i/o51 i/o52 i/o53 i/o54 i/o55 gnd i/o56 i/o57 i/o58 i/o59 v cc gnd gnd v cc i/o60 i/o61 i/o62 i/o63 gnd i/o64 i/o65 i/o66 i/o67 i/o68 i/o69 i/o70 i/o71 v cc gnd i/o72 i/o73 i/o74 i/o75 i/o76 i/o77 i/o78 i/o79 gnd 1a7 1a6 1a5 1a4 1a3 1a2 1a1 1a0 1d2 1d3 1d4 1d5 1d6 1d7 1d8 1d9 1d10 1d11 1d12 1d13 2d13 2d12 2d11 2d10 2d9 2d8 2d7 2d6 2d5 2d4 2d3 2d2 2a0 2a1 2a2 2a3 2a4 2a5 2a6 2a7 gnd i/o159 i/o158 i/o157 i/o156 i/o155 i/o154 i/o153 i/o152 gnd v cc i/o151 i/o150 i/o149 i/o148 i/o147 i/o146 i/o145 i/o144 gnd i/o143 i/o142 i/o141 i/o140 v cc gnd gnd v cc i/o139 i/o138 i/o137 i/o136 gnd i/o135 i/o134 i/o133 i/o132 i/o131 i/o130 i/o129 i/o128 v cc gnd i/o127 i/o126 i/o125 i/o124 i/o123 i/o122 i/o121 i/o120 gnd 0a7 0a6 0a5 0a4 0a3 0a2 0a1 0a0 0d2 0d3 0d4 0d5 0d6 0d7 0d8 0d9 0d10 0d11 0d12 0d13 3d13 3d12 3d11 3d10 3d9 3d8 3d7 3d6 3d5 3d4 3d3 3d2 3a0 3a1 3a2 3a3 3a4 3a5 3a6 3a7 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 20446g-023 3d15 clk = clock gnd = ground i= input i/o = input/output nc = no connect v cc = supply voltage tdi = test data in tck = test clock tms = test mode select tdo = test data out pin designations macrocell (0-15) p al block (a-d) segment (0-3)
36 mach 5 family 208-pin pqfp (with internal heat spreader) connection diagram t op view 208-pin pqfp (320, 384, 512 macrocells) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 tdi i/o0 i/o1 i/o2 i/o3 i/o4 i/o5 i/o6 i/o7 v cc gnd i/o8 i/o9 i/o10 i/o11 i/o12 i/o13 i/o14 i/o15 gnd i/o16 i/o17 i/o18 i/o19 i0/clk0 v cc gnd i1/clk1 i/o20 i/o21 i/o22 i/o23 gnd i/o24 i/o25 i/o26 i/o27 i/o28 i/o29 i/o30 i/o31 gnd v cc i/o32 i/o33 i/o34 i/o35 i/o36 i/o37 i/o38 i/o39 tck 0a2 0a3 0a4 0a7 0a8 0a11 0a12 0a13 0d15 0d14 0d13 0d12 0d11 0d10 0d9 0d8 0d7 0d4 0d3 0d2 1d2 1d3 1d4 1d7 1d8 1d9 1d10 1d11 1d12 1d13 1d14 1d15 1a13 1a12 1a11 1a8 1a7 1a4 1a3 1a2 0a2 0a3 0a4 0a7 0a8 0a11 0a12 0a13 0d15 0d14 0d13 0d12 0d11 0d10 0d9 0d8 0d7 0d4 0d3 0d2 1d2 1d3 1d4 1d7 1d8 1d9 1d10 1d11 1d12 1d13 1d14 1d15 1a13 1a12 1a11 1a8 1a7 1a4 1a3 1a2 0a2 0a3 0a4 0a7 0a8 0a11 0a12 0a13 0d15 0d14 0d13 0d12 0d11 0d10 0d9 0d8 0d7 0d4 0d3 0d2 1d2 1d3 1d4 1d7 1d8 1d9 1d10 1d11 1d12 1d13 1d14 1d15 1a15 1a14 1a13 1a12 1a11 1a10 1a9 1a8 tdo i/o119 i/o118 i/o117 i/o116 i/o115 i/o114 i/o113 i/o112 v cc gnd i/o111 i/o110 i/o109 i/o108 i/o107 i/o106 i/o105 i/o104 gnd i/o103 i/o102 i/o101 i/o100 i3/clk3 gnd v cc i2/clk2 i/o99 i/o98 i/o97 i/o96 gnd i/o95 i/o94 i/o93 i/o92 i/o91 i/o90 i/o89 i/o88 gnd v cc i/o87 i/o86 i/o85 i/o84 i/o83 i/o82 i/o81 i/o80 tms 5a2 5a3 5a4 5a7 5a8 5a11 5a12 5a13 5d15 5d14 5d13 5d12 5d11 5d10 5d9 5d8 5d7 5d4 5d3 5d2 4d2 4d3 4d4 4d7 4d8 4d9 4d10 4d11 4d12 4d13 4d14 4d15 4a13 4a12 4a11 4a8 4a7 4a4 4a3 4a2 4a2 4a3 4a4 4a7 4a8 4a11 4a12 4a13 4d15 4d14 4d13 4d12 4d11 4d10 4d9 4d8 4d7 4d4 4d3 4d2 3d2 3d3 3d4 3d7 3d8 3d9 3d10 3d11 3d12 3d13 3d14 3d15 3a13 3a12 3a11 3a8 3a7 3a4 3a3 3a2 3a2 3a3 3a4 3a7 3a8 3a11 3a12 3a13 3d15 3d14 3d13 3d12 3d11 3d10 3d9 3d8 3d7 3d4 3d3 3d2 2d2 2d3 2d4 2d7 2d8 2d9 2d10 2d11 2d12 2d13 2d14 2d15 2a15 2a14 2a13 2a12 2a11 2a10 2a9 2a8 m5-384 m5lv-384 m5-384 m5lv-384 m5-384 m5lv-384 m5-384 m5lv-384 m5-320 m5lv-320 m5-320 m5lv-320 m5-320 m5lv-320 m5-320 m5lv-320 m5-512 m5lv-512 m5-512 m5lv-512 m5-512 m5lv-512 m5-512 m5lv-512 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 gnd i/o40 i/o41 i/o42 i/o43 i/o44 i/o45 i/o46 i/o47 gnd v cc i/o48 i/o49 i/o50 i/o51 i/o52 i/o53 i/o54 i/o55 gnd i/o56 i/o57 i/o58 i/o59 v cc gnd gnd v cc i/o60 i/o61 i/o62 i/o63 gnd i/o64 i/o65 i/o66 i/o67 i/o68 i/o69 i/o70 i/o71 v cc gnd i/o72 i/o73 i/o74 i/o75 i/o76 i/o77 i/o78 i/o79 gnd 2a13 2a12 2a11 2a8 2a7 2a4 2a3 2a2 2b0 2b1 2b2 2b3 2b4 2b5 2b6 2b7 2b8 2b11 2b12 2b13 3b13 3b12 3b11 3b8 3b7 3b6 3b5 3b4 3b3 3b2 3b1 3b0 3a2 3a3 3a4 3a7 3a8 3a11 3a12 3a13 1b2 1b3 1b4 1b7 1b8 1b11 1b12 1b13 2a15 2a14 2a13 2a12 2a11 2a10 2a9 2a8 2a7 2a4 2a3 2a2 2b2 2b3 2b4 2b7 2b8 2b9 2b10 2b11 2b12 2b13 2b14 2b15 3b13 3b12 3b11 3b8 3b7 3b4 3b3 3b2 1a7 1a6 1a5 1a4 1a3 1a2 1a1 1a0 1b0 1b1 1b2 1b3 1b4 1b5 1b6 1b7 1b8 1b11 1b12 1b13 2b13 2b12 2b11 2b8 2b7 2b6 2b5 2b4 2b3 2b2 2b1 2b0 2a0 2a1 2a2 2a3 2a4 2a5 2a6 2a7 gnd i/o159 i/o158 i/o157 i/o156 i/o155 i/o154 i/o153 i/o152 gnd v cc i/o151 i/o150 i/o149 i/o148 i/o147 i/o146 i/o145 i/o144 gnd i/o143 i/o142 i/o141 i/o140 v cc gnd gnd v cc i/o139 i/o138 i/o137 i/o136 gnd i/o135 i/o134 i/o133 i/o132 i/o131 i/o130 i/o129 i/o128 v cc gnd i/o127 i/o126 i/o125 i/o124 i/o123 i/o122 i/o121 i/o120 gnd 7a13 7a12 7a11 7a8 7a7 7a4 7a3 7a2 7b0 7b1 7b2 7b3 7b4 7b5 7b6 7b7 7b8 7b11 7b12 7b13 6b13 6b12 6b11 6b8 6b7 6b6 6b5 6b4 6b3 6b2 6b1 6b0 6a2 6a3 6a4 6a7 6a8 6a11 6a12 6a13 0b2 0b3 0b4 0b7 0b8 0b11 0b12 0b13 5a15 5a14 5a13 5a12 5a11 5a10 5a9 5a8 5a7 5a4 5a3 5a2 5b2 5b3 5b4 5b7 5b8 5b9 5b10 5b11 5b12 5b13 5b14 5b15 4b13 4b12 4b11 4b8 4b7 4b4 4b3 4b2 0b2 0b3 0b4 0b7 0b8 0b11 0b12 0b13 4a15 4a14 4a13 4a12 4a11 4a10 4a9 4a8 4a7 4a4 4a3 4a2 4b2 4b3 4b4 4b7 4b8 4b9 4b10 4b11 4b12 4b13 4b14 4b15 3b13 3b12 3b11 3b8 3b7 3b4 3b3 3b2 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 20446g-024 7d15 clk = clock gnd = ground i= input i/o = input/output nc = no connect v cc = supply voltage tdi = test data in tck = test clock tms = test mode select tdo = test data out pin designations macrocell (0-15) p al block (a-d) segment (0-7)
mach 5 family 37 256-ball bga connection diagram ?m5-320 bottom view (i/o pin-outs) 256-ball bga 20 19 18 17 16 15 14 13 12 11 10 987654321 a gnd i/o11 gnd i/o44 i/o58 gnd i/o70 i/o76 gnd gnd gnd gnd i/o108 i/o116 gnd i/o128 i/o134 gnd gnd gnd a b gnd i/o12 i/o28 i/o45 i/o59 i/o64 i/o71 i/o77 i/o84 i/o90 i/o96 i/o102 i/o109 i/o117 i/o122 i/o129 i/o135 i/o148 i/o164 gnd b c i/o0 i/o13 v cc i/o46 i/o60 i/o65 i/o72 i/o78 i/o85 i/o91 i/o97 i/o103 i/o110 i/o118 i/o123 i/o130 i/o136 v cc i/o165 i/o181 c d i/o1 i/o14 i/o29 v cc v cc i/o66 v cc i/o79 i/o86 i/o92 i/o98 i/o104 i/o111 v cc i/o124 v cc v cc i/o149 i/o166 i/o182 d e i/o2 i/o15 i/o30 tdi tdo i/o150 i/o167 i/o183 e f gnd i/o16 i/o31 i/o47 i/o137 i/o151 i/o168 gnd f g i/o3 i/o17 i/o32 v cc v cc i/o152 i/o169 i/o184 g h gnd i/o18 i/o33 i/o48 i/o138 i/o153 i/o170 gnd h j i/o4 i/o19 i/o34 i/o49 i/o139 i/o154 i/o171 i/o185 j k gnd io/clk0 i/o35 i/o50 i/o140 i/o155 i3/clk3 i/o186 k l i/o5 i1/clk1 i/o36 i/o51 i/o141 i/o156 i2/clk2 gnd l m i/o6 i/o20 i/o37 i/o52 i/o142 i/o157 i/o172 i/o187 m n gnd i/o21 i/o38 i/o53 i/o143 i/o158 i/o173 gnd n p i/o7 i/o22 i/o39 v cc v cc i/o159 i/o174 i/o188 p r gnd i/o23 i/o40 i/o54 i/o144 i/o160 i/o175 gnd r t i/o8 i/o24 i/o41 tck tms i/o161 i/o176 i/o189 t u i/o9 i/o25 i/o42 v cc v cc i/o67 v cc i/o80 i/o87 i/o93 i/o99 i/o105 i/o112 v cc i/o125 v cc v cc i/o162 i/o177 i/o190 u v i/o10 i/o26 v cc i/o55 i/o61 i/o68 i/o73 i/o81 i/o88 i/o94 i/o100 i/o106 i/o113 i/o119 i/o126 i/o131 i/o145 v cc i/o178 i/o191 v w gnd i/o27 i/o43 i/o56 i/o62 i/o69 i/o74 i/o82 i/o89 i/o95 i/o101 i/o107 i/o114 i/o120 i/o127 i/o132 i/o146 i/o163 i/o179 gnd w y gnd gnd gnd i/o57 i/o63 gnd i/o75 i/o83 gnd gnd gnd gnd i/o115 i/o121 gnd i/o133 i/o147 gnd i/o180 gnd y 20 19 18 17 16 15 14 13 12 11 10 987654321 20446g-026 clk = clock gnd = ground i= input i/o = input/output nc = no connect v cc = supply voltage tdi = test data in tck = test clock tms = test mode select tdo = test data out pin designations
38 mach 5 family 256-ball bga connection diagram ?m5-320 bottom view (macrocell association) 256-ball bga 20 19 18 17 16 15 14 13 12 11 10 987654321 a gnd 0b2 gnd 0b13 4a14 gnd 4a8 4a4 gnd gnd gnd gnd 4b4 4b8 gnd 4b14 3b13 gnd gnd gnd a b gnd 0a3 0b8 0b11 4a15 4a11 4a10 4a6 4a3 4a0 4b0 4b3 4b6 4b10 4b11 4b15 3b11 3b8 3b2 gnd b c 0d15 0a8 v cc 0b3 0b4 0b12 4a13 4a9 4a5 4a1 4b1 4b5 4b9 4b13 3b12 3b4 3b3 v cc 3a3 3a11 c d 0d13 0a11 0a2 v cc v cc 0b7 v cc 4a12 4a7 4a2 4b2 4b7 4b12 v cc 3b7 v cc v cc 3a2 3a8 3d15 d e 0d10 0a13 0a4 tdi tdo 3a4 3a13 3d12 e f gnd 0d12 0a12 0a7 3a7 3a12 3d13 gnd f g 0d7 0d8 0d14 v cc v cc 3d14 3d9 3d7 g h gnd 0d4 0d9 0d11 3d11 3d10 3d8 gnd h j 0d2 0d3 0d5 0d6 3d6 3d5 3d4 3d3 j k gnd io/clk0 0d0 0d1 3d1 3d0 i3/clk3 3d2 k l 1d2 i1/clk1 1d0 1d1 2d1 2d0 i2/clk2 gnd l m 1d3 1d4 1d5 1d6 2d6 2d5 2d3 2d2 m n gnd 1d8 1d10 1d11 2d11 2d9 2d4 gnd n p 1d7 1d9 1d14 v cc v cc 2d14 2d8 2d7 p r gnd 1d13 1a14 1a11 2a11 2a14 2d12 gnd r t 1d12 1a15 1a10 tck tms 2a10 2a15 2d10 t u 1d15 1a12 1a8 v cc v cc 1a4 v cc 1b3 1b8 1b13 2b13 2b8 2b3 v cc 2a4 v cc v cc 2a8 2a13 2d13 u v 1a13 1a9 v cc 1a6 1a5 1a1 1b2 1b6 1b10 1b14 2b14 2b10 2b6 2b2 2a1 2a5 2a6 v cc 2a12 2d15 v w gnd 1a7 1a3 1a2 1b0 1b4 1b5 1b9 1b12 1b15 2b15 2b12 2b9 2b5 2b4 2b0 2a2 2a3 2a9 gnd w y gnd gnd gnd 1a0 1b1 gnd 1b7 1b11 gnd gnd gnd gnd 2b11 2b7 gnd 2b1 2a0 gnd 2a7 gnd y 20 19 18 17 16 15 14 13 12 11 10 987654321 20446g-029 clk = clock gnd = ground i= input i/o = input/output nc = no connect v cc = supply voltage tdi = test data in tck = test clock tms = test mode select tdo = test data out pin designations 4d15 macrocell (0-15) p al block (a-d) segment (0-4)
mach 5 family 39 352-ball bga connection diagram ?m5-512, m5lv-512 bottom view (i/o pin-outs) 352-ball bga 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 987654321 a nc gnd nc i/o51 gnd i/o73 i/o80 i/o87 gnd i/o101 nc i/o114 gnd i/o128 i/o134 i/o142 gnd i/o156 i/o162 gnd nc gnd nc gnd nc nc a b nc gnd nc i/o52 i/o68 i/o74 i/o81 i/o88 i/o95 i/o102 i/o107 i/o115 i/o122 i/o129 i/o135 i/o143 i/o150 i/o157 i/o163 i/o169 i/o176 i/o183 i/o188 gnd nc n c b c gnd i/o11 tdi i/o53 i/o69 i/o75 i/o82 i/o89 i/o96 i/o103 i/o108 i/o116 i/o123 i/o130 i/o136 i/o144 i/o151 i/o158 i/o164 i/o170 i/o177 i/o184 nc nc nc nc c d i/o0 i/o12 i/o32 v cc i/o70 i/o76 i/o83 i/o90 v cc i/o104 i/o109 i/o117 v cc i/o131 i/o137 i/o145 v cc i/o159 i/o165 i/o171 i/o178 v cc tdo i/o205 i/o224 gnd d e nc i/o13 i/o33 i/o54 i/o189 i/o206 i/o225 nc e f gnd i/o14 i/o34 i/o55 i/o190 i/o207 i/o226 i/o245 f g i/o1 i/o15 i/o35 v cc i/o191 i/o208 i/o227 gnd g h i/o2 i/o16 i/o36 i/o56 v cc i/o209 i/o228 i/o246 h j gnd i/o17 i/o37 v cc i/o192 i/o210 i/o229 i/o247 j k i/o3 i/o18 i/o38 i/o57 v cc i/o211 i/o230 gnd k l i/o4 i/o19 i/o39 i/o58 i/o193 i/o212 i/o231 i/o248 l m i/o5 i/o20 i/o40 i/o59 i/o194 i/o213 i/o232 i/o249 m n gnd i/o21 i0/clk0 v cc i/o195 i/o214 i/o233 i3/clk3 n p i1/clk1 i/o22 i/o41 i/o60 v cc i2clk2 i/o234 gnd p r i/o6 i/o23 i/o42 i/o61 i/o196 i/o215 i/o235 i/o250 r t i/o7 i/o24 i/o43 i/o62 i/o197 i/o216 i/o236 i/o251 t u gnd i/o25 i/o44 v cc i/o198 i/o217 i/o237 i/o252 u v i/o8 i/o26 i/o45 i/o63 v cc i/o218 i/o238 gnd v w i/o9 i/o27 i/o46 v cc i/o199 i/o219 i/o239 i/o253 w y gnd i/o28 i/o47 i/o64 v cc i/o220 i/o240 i/o254 y a a i/o10 i/o29 i/o48 i/o65 i/o200 i/o221 i/o241 gnd aa a b nc i/o30 i/o49 i/o66 i/o201 i/o222 i/o242 nc ab a c gnd i/o31 i/o50 tck v cc i/o77 i/o84 i/o91 i/o97 v cc i/o110 i/o118 i/o124 v cc i/o138 i/o146 i/o152 v cc i/o166 i/o172 i/o179 i/o185 v cc i/o223 i/o243 i/o255 ac a d nc nc nc nc i/o71 i/o78 i/o85 i/o92 i/o98 i/o105 i/o111 i/o119 i/o125 i/o132 i/o139 i/o147 i/o153 i/o160 i/o167 i/o173 i/o180 i/o186 i/o202 tms i/o244 g nd ad a e nc nc gnd i/o67 i/o72 i/o79 i/o86 i/o93 i/o99 i/o106 i/o112 i/o120 i/o126 i/o133 i/o140 i/o148 i/o154 i/o161 i/o168 i/o174 i/o181 i/o187 i/o203 nc gnd n c ae a f nc nc gnd nc gnd nc gnd i/o94 i/o100 gnd i/o113 i/o121 i/o127 gnd i/o141 i/o149 i/o155 gnd nc i/o175 i/o182 gnd i/o204 nc gnd nc af 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 987654321 20446g-030 clk = clock gnd = ground i= input i/o = input/output nc = no connect v cc = supply voltage tdi = test data in tck = test clock tms = test mode select tdo = test data out pin designations
40 mach 5 family 352-ball bga connection diagram ?m5-512, m5lv-512 bottom view (macrocell association) 352-ball bga 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 987654321 a nc gnd nc 7a10 gnd 7a5 7a0 7b1 gnd 7b7 nc 7b14 gnd 6b14 6b10 6b6 gnd 6b1 6a1 gnd nc gnd nc gnd nc nc a b nc gnd nc 7a13 7a9 7a6 7a2 7b0 7b3 7b6 7b10 7b13 7b15 6b13 6b9 6b5 6b2 6a0 6a4 6a6 6a9 6a12 6a14 gnd nc nc b c gnd 0a1 tdi 7a14 7a11 7a7 7a3 7a1 7b2 7b5 7b9 7b12 6b15 6b12 6b8 6b4 6b0 6a2 6a5 6a8 6a10 6a13 nc nc nc nc c d 0a6 0a3 0a2 v cc 7a15 7a12 7a8 7a4 v cc 7b4 7b8 7b11 v cc 6b11 6b7 6b3 v cc 6a3 6a7 6a11 6a15 v cc tdo 5a1 5a2 gnd d e nc 0a8 0a5 0a0 5a0 5a4 5a5 nc e f gnd 0a9 0a7 0a4 5a3 5a7 5a9 5a12 f g 0a13 0a12 0a10 v cc 5a6 5a8 5a14 gnd g h 0d15 0a15 0a14 0a11 v cc 5a10 5a15 5d15 h j gnd 0d13 0d14 v cc 5a11 5a13 5d13 5d11 j k 0d9 0d10 0d11 0d12 v cc 5d 14 5d10 gnd k l 0d5 0d6 0d7 0d8 5d12 5d9 5d8 5d6 l m 0d1 0d2 0d4 0d3 5d7 5d5 5d4 5d3 m n gnd 0d0 i0/clk0 v cc 5d2 5d1 5d0 i3/clk3 n p i1/clk1 1d0 1d1 1d2 v cc i2/clk2 4d0 gnd p r 1d3 1d4 1d5 1d7 4d3 4d4 4d2 4d1 r t 1d6 1d8 1d9 1d12 4d8 4d7 4d6 4d5 t u gnd 1d10 1d14 v cc 4d12 4d11 4d10 4d9 u v 1d11 1d13 1a13 1a11 v cc 4d14 4d13 gnd v w 1d15 1a15 1a10 v cc 4a11 4a14 4a15 4d15 w y gnd 1a14 1a8 1a6 v cc 4a10 4a12 4a13 y a a 1a12 1a9 1a7 1a3 4a4 4a7 4a9 gnd aa a b nc 1a5 1a4 1a0 4a0 4a5 4a8 nc ab ac gnd 1a2 1a1 tck v cc 2a15 2a11 2a7 2a3 v cc 2b3 2b7 2b11 v cc 3b11 3b7 3b3 v cc 3a2 3a6 3a10 3a14 v cc 4a2 4a3 4a6 ac a d nc nc nc nc 2a13 2a10 2a8 2a5 2a2 2b0 2b4 2b8 2b12 2b15 3b12 3b8 3b4 3b1 3a1 3a4 3a8 3a11 3a15 tms 4a1 gnd ad ae nc nc gnd 2a14 2a12 2a9 2a6 2a4 2a0 2b2 2b5 2b9 2b13 3b15 3b13 3b9 3b5 3b2 3b0 3a3 3a7 3a9 3a13 nc gnd nc ae af nc nc gnd nc gnd nc gnd 2a1 2b1 gnd 2b6 2b10 2b14 gnd 3b14 3b10 3b6 gnd nc 3a0 3a5 gnd 3a12 nc gnd nc af 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 987654321 20446g-031 clk = clock gnd = ground i= input i/o = input/output nc = no connect v cc = supply voltage tdi = test data in tck = test clock tms = test mode select tdo = test data out pin designations 7d15 macrocell (0-15) p al block (a-d) segment (0-7)
mach 5 family 41 5v m5 ordering information 1,2 lattice standard products are available in several packages and operating ranges. the order number (valid combination) is forme d by a combination of the elements below. . device marking actual device marking differs from the ordering part number (opn). all mach devices are dual-marked with both commercial and industrial grades. the industrial grade is slower, i.e., m5-512/256-7ac-10ai. . v alid combinations v alid combinations list con?urations planned to be supported in volume for this device. consult the local lattice sales of?e to con?m availability of speci? valid combinations and to check on newly released combinations. f amily type m5- = mach 5 (5-v v cc ) m5- 512 /256 -7 sa c macrocell density 128 = 128 macrocells 192 = 192 macrocells 256 = 256 macrocells 320 = 320 macrocells 384 = 384 macrocells 512 = 512 macrocells i/os /68 = 68 i/os in 100-pin pqfp or tqfp /104 = 104 i/os in 144-pin pqfp or tqfp /120 = 120 i/os in 160-pin pqfp /160 = 160 i/os in 208-pin pqfp /192 = 192 i/os in 256-ball bga /256 = 256 i/os in 352-ball bga operating conditions c= commercial (0 c to +70 c) i= industrial (-40 c to +85 c) p ackage type y= plastic quad flat pack (pqfp) v= thin quad flat pack (tqfp) sa = ball grid array (bga) speed -5 = 5.5 ns t pd -6 = 6.5 ns t pd -7 = 7.5 ns t pd -10 = 10 ns t pd -12 = 12 ns t pd -15 = 15 ns t pd -20 = 20 ns t pd note: 1. see below for valid device/package combinations. 2. m5-128/1, m5-192/1 and m5-256/1 recommended for new designs. programming designator blank = initial algorithm /1 = first revision v alid combinations m5-128/68 commercial: -5, -7, -10, -12, -15 industrial: -7, -10, -12, -15, -20 yc, vc, yi, vi m5-128/104 yc, yi m5-128/120 yc, yi m5-192/68 vc, vi m5-192/120 yc, yi m5-256/68 vc, vi m5-256/120 yc, yi m5-256/160 yc, yi v alid combinations m5-320/160 commercial: -6, -7, -10, -12, -15 industrial: -7, -10, -12, -15, -20 yc, yi m5-320/192 sac, sai, m5-384/160 yc, yi m5-512/160 yc, yi m5-512/256 sac, sai
42 mach 5 family 3.3v m5lv ordering information 1 lattice standard products are available in several packages and operating ranges. the order number (valid combination) is forme d by a combination of the elements below. device marking actual device marking differs from the ordering part number (opn). all mach devices are dual-marked with both commercial and industrial grades. the industrial grade is slower, i.e., m5lv-512/256-7ac-10ai. v alid combinations v alid combinations list con?urations planned to be supported in volume for this device. consult the local lattice sales of?e to con?m availability of speci? valid combinations and to check on newly released combinations. f amily type m5lv- = mach 5 low voltage (3.3-v v cc ) m5lv- 512 /256 -7 sa c macrocell density 128 = 128 macrocells 256 = 256 macrocells 320 = 320 macrocells 384 = 384 macrocells 512 = 512 macrocells i/os /68 = 68 i/os in 100-pin pqfp or tqfp /74 = 74 i/os in 100-pin tqfp /104 = 104 i/os in 144-pin pqfp or tqfp /120 = 120 i/os in 160-pin pqfp /160 = 160 i/os in 208-pin pqfp /256 = 256 i/os in 352-ball bga operating conditions c= commercial (0 c to +70 c) i= industrial (-40 c to +85 c) p ackage type y= plastic quad flat pack (pqfp ) v= thin quad flat pack (tqfp) sa = ball grid array (bga) speed -5 = 5.5 ns t pd -6 = 6.5 ns t pd -7 = 7.5 ns t pd -10 = 10 ns t pd -12 = 12 ns t pd -15 = 15 ns t pd -20 = 20 ns t pd note: 1. see below for valid device/package combinations. v alid combinations m5lv-128/68 commercial: -5, -7, -10, -12 industrial: -7, -10, -12, -15 vc, vi m5lv-128/74 vc, vi m5lv-128/104 vc, vi m5lv-128/120 yc, yi m5lv-256/68 yc, yi m5lv-256/74 vc, vi m5lv-256/104 vc, vi m5lv-256/120 yc, yi m5lv-256/160 yc, yi v alid combinations m5lv-320/120 commercial: -6, -7, -10, -12, -15 industrial: -10, -12, -15, -20 yc, yi m5lv-320/160 yc, yi m5lv-384/120 yc, yi m5lv-384/160 yc, yi m5lv-512/120 yc, yi m5lv-512/160 yc, yi m5lv-512/256 sac, sai

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